CY7C1360V25 Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1360V25 Datasheet PDF : 31 Pages
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PRELIMINARY
CY7C1360V25
CY7C1362V25
CY7C1364V25
Pin Definitions (119-Ball BGA)
x18 Pin Locations x36 Pin Locations
4P, 4N, 2A, 3A, 5A,
6A, 3B, 5B, 2C, 3C,
5C, 6C, 2R, 6R, 2T,
3T, 5T, 6B, 6T
4P, 4N,
2A, 2C, 2R, 3A, 3B,
3C, 3T, 4T, 5A, 5B,
5C, 5T, 6A, 6B, 6C,
6R
5L, 3G
5L, 5G, 3G, 3L
4M
4M
Name
A0
A1
A
BWa
BWb
BWc
BWd
GW
4H
4H
4K
4K
BWE
CLK
4E
4E
CE1
97
97
CE2
92
92
CE3
4F
4F
OE
4G
4G
4A
4A
ADV
ADSP
4B
4B
ADSC
I/O
Input-
Synchronous
Input-
Synchronous
Description
Address Inputs used to select one of the address
locations. Sampled at the rising edge of the CLK if
ADSP or ADSC is active LOW, and CE1, CE2, and
CE3 are sampled active. A[1:0] feed the 2-bit
counter.
Byte Write Select Inputs, active LOW. Qualified with
BWE to conduct byte writes to the SRAM. Sampled
on the rising edge of CLK.
Input-
Synchronous
Input-
Synchronous
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Global Write Enable Input, active LOW. When as-
serted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regard-
less of the values on BWa,b,c,d and BWE).
Byte Write Enable Input, active LOW. Sampled on
the rising edge of CLK. This signal must be assert-
ed LOW to conduct a byte write.
Clock Input. Used to capture all synchronous inputs
to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst
operation.
Chip Enable 1 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE2
and CE3 to select/deselect the device. ADSP is ig-
nored if CE1 is HIGH.
Chip Enable 2 Input, active HIGH. Sampled on the
rising edge of CLK. Used in conjunction with CE1
and CE3 to select/deselect the device. This pin is
also used for expansion to a 16M density SRAM.
Chip Enable 3 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE1
and CE2 to select/deselect the device.
Output Enable, asynchronous input, active LOW.
Controls the direction of the I/O pins. When LOW,
the I/O pins behave as outputs. When deasserted
HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the first clock of a
read cycle when emerging from a deselected state.
Advance Input signal, sampled on the rising edge
of CLK. When asserted, it automatically increments
the address in a burst cycle.
Address Strobe from Processor, sampled on the
rising edge of CLK. When asserted LOW, A is cap-
tured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
Address Strobe from Controller, sampled on the ris-
ing edge of CLK. When asserted LOW, A[x:0] is cap-
tured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized.
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