ML4425 Ver la hoja de datos (PDF) - Micro Linear Corporation
Número de pieza
componentes Descripción
Fabricante
ML4425 Datasheet PDF : 16 Pages
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ML4425
CRR
TO
SPEED FB
FILTER
CAT
CRT
FB A
FB B
FB C
VDD CAT
750nA
–
1.5V
+
BACK
EMF
SAMPLER
VDD
CRT
750nA
–
1.5V
+
TO RESET INPUT
OF COMMUTATION
STATE MACHINE
CRR
SPEED CVCO
FB
RVCO
VDD
500nA
VOLTAGE
CONTROLLED
OSCILLATOR
VCO/TACH
Figure 8. ML4425 Start-up Circuitry for Controlling the Align and Ramp Times
Run Mode (Back EMF Sensing)
At the end of ramp mode the controller goes into run
mode. In run mode, the back EMF sensing is enabled and
commutation is now under the control of the phase locked
loop. Motor speed is now regulated by the speed control
loop.
PWM SPEED CONTROL
Speed control is accomplished by setting a speed
command at SPEED SET with an input voltage from 0 to
6.9V (VREF). The accuracy of the speed command is
determined by the external components RVCO and CVCO.
There are a number of methods that can be used to control
the speed command of the ML4425. One is to use a 10kW
potentiometer from VREF to ground with the wiper
connected to SPEED SET. If SPEED SET is controlled from
a microcontroller, one of its DACs can be used with VREF
as its input reference.
The speed command is compared with the sensed speed
from SPEED FB through a transconductance error
amplifier. The output of the speed error amplifier is SPEED
COMP. SPEED COMP is clamped between one diode drop
above 3.9V (approximately 4.6V) and one diode drop
below 1.7V (approximately 1V) to prevent speed loop
“wind-up”. Speed loop compensation components are
connected to this pin as shown in Figure 9. The speed loop
compensation components are calculated as follows:
CSC
=
fSB
26.9 N VMOTOR CVCO
Ke 2.5 + 98.696 tm2 fSB2
(9a)
RSC
=
2p
10
fSB
CSC
(9b)
Where fSB is the speed loop bandwidth in Hz.
VREF
10kΩ
RSC
CSC
CT
FROM
SPEED FB
+
–
SPEED SET
3.9V
–
SPEED COMP
+
1.7V
TO
GATING
LOGIC &
OUTPUT
DRIVERS
CT
1.7V
20kHz
PWM ON/OFF
FROM ILIMIT
ONE-SHOT
Figure 9. Speed Control Loop Component Connections
The voltage on SPEED COMP is compared with a ramp
oscillator to create a PWM duty cycle. The PWM ramp
oscillator creates a sawtooth function from 1.7V to 3.9V
as shown in Figure 9. A negative clamp at one diode drop
below 1.7V (approximately 1V) starts the oscillator on
power up. The frequency of the ramp oscillator is set by a
capacitor to ground CIOS and is selected using the
following equation:
1 50mA
CT
=
fPWM
2.4V
(10)
Where fPWM is the PWM frequency in Hz. The PWM duty
cycle from the speed control loop is gated the current
limit one shot that controls the LA, LB, and LC output
drivers.
11
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