WT6016 Ver la hoja de datos (PDF) - Weltrend Semiconductor
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WT6016 Datasheet PDF : 24 Pages
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SYNC Processor
WT6016
Digital Monitor Controller
Ver. 1.51 Jul-31-1998
The SYNC processor can : (1) separate the composite sync signal; (2) calculate HSYNC and
VSYNC frequencies; (3) detect polarities of HSYNC and VSYNC inputs; (4) control the output
polarities of HSO and VSO pins. (5) generate free-running horizontal and vertical sync signals for
burn-in test; (6) generate self-test pattern signal.
HSYNC
H Polarity
detect
Mux
Sync
Separator
H+V
H/V SYNC
H
Generator
V
Mux
VSYNC
H+V
Mux
SELF
Mux
H/V Freq. Counter
H Polarity
Control
V Polarity
detect & control
HSO
VSO
Test Pattern
Mux
Generator PB3
PB3/PAT
Composite Sync Signal Separation
The composite sync signal comes from HSYNC pin and is separated by the sync separator.
The operations of sync separator are:
- detect the polarity and convert composite sync signal to positive polarity.
- extract Vsync
Pulse width less than 8us will be filtered, but the Vsync will be widened about 8us.
- count the pulses during the separated Vsync is low and save the counter value (NH).
- bypass the composite sync pulses before the counter equals to NH.
- start inserting Hsync pulses after the counter equals to NH until the separated Vsync is low.
- the period of inserted Hsync is decided by the last two bypassed Hsync.
- the pulse width of the inserted Hsync is 2us.
Positive H+V
separated Hsync
separated Vsync
bypass
insert HSYNC
To decide whether the HSYNC input is a composite sync signal or not, program should check the
frequency of VSYNC first (reset H+V bit to “0”). If the VSYNC frequency is lower than 15.25Hz
(OVF2=1), set H+V bit to “1” and check VSYNC frequency again. If VSYNC still has no frequency,
that is power saving condition, program should reset H+V bit. If it has a valid frequency, the HSYNC
input is composite signal.
Weltrend Semiconductor, Inc.
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