M95256-CS3G Ver la hoja de datos (PDF) - STMicroelectronics

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componentes Descripción

Fabricante

M95256-CS3G

256 Kbit serial SPI bus EEPROM with high-speed clock

STMicroelectronics 

M95256-DR, M95256, M95256-W, M95256-R

Operating features

3.8.3

therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see

Figure 17).

In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge

sensitive as well as level sensitive: after power-up, the device does not become selected

until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select

(S) must have been High, prior to going Low to start the first operation.

The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage

defined in Table 8, Table 9 and Table 10 and the rise time must not vary faster than 1 V/µs.

Power-down

During Power-down (continuous decrease of VCC supply voltage below the minimum VCC

operating voltage defined in Table 8, Table 9 and Table 10), the device must be:

● deselected (Chip Select S should be allowed to follow the voltage applied on VCC)

● in Standby Power mode (there should not be an internal Write cycle in progress).

4

Operating features

4.1

Hold condition

The Hold (HOLD) signal is used to pause any serial communications with the device without

resetting the clocking sequence.

During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data

input (D) and Serial Clock (C) are Don’t Care.

To enter the Hold condition, the device must be selected, with Chip Select (S) low.

Normally, the device is kept selected, for the whole duration of the Hold condition.

Deselecting the device while it is in the Hold condition, has the effect of resetting the state of

the device, and this mechanism can be used if it is required to reset any processes that had

been in progress.

The Hold condition starts when the Hold (HOLD) signal is driven low at the same time as

Serial Clock (C) already being low (as shown in Figure 5).

The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as

Serial Clock (C) already being low.

Figure 5 also shows what happens if the rising and falling edges are not timed to coincide

with Serial Clock (C) being low.

Doc ID 12276 Rev 11

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