PA7572 Ver la hoja de datos (PDF) - Anachip Corporation
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PA7572 Datasheet PDF : 10 Pages
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Inside the Logic Array
The heart of the PEEL™ Array architecture is based on a
logic array structure similar to that of a PLA (programmable
AND, programmable OR). The logic array implements all
logic functions and provides interconnection and control of
the cells. In the PA7572 PEEL™ Array, 62 inputs are
available into the array from the I/O cells, inputs cells and
input/global-clock pins.
All inputs provide both true and complement signals, which
can be programmed to any product term in the array. The
PA7572 PEEL™ Arrays contains 124 product terms. All
product terms (with the exception of certain ones fed to the
global cells) can be programmably connected to any of the
sum-terms of the logic control cells (four sum-terms per
logic control cell). Product-terms and sum-terms are also
routed to the global cells for control purposes. Figure 3
shows a detailed view of the logic array structure.
From
IO Cells
(IO C ,IN C ,
I/CLK)
62 Array Inputs
products functions provided to the logic cells can be used for
clocks, resets, presets and output enables instead of just
simple product-term control.
The PEEL™ logic array can also implement logic functions
with many product terms within a single-level delay. For
example a 16-bit comparator needs 32 shared product terms
to implement 16 exclusive-OR functions. The PEEL™ logic
array easily handles this in a single level delay. Other
PLDs/CPLDs either run out of product-terms or require
expanders or additional logic levels that often slow
performance and skew timing.
Logic Control Cell (LCC)
Logic Control Cells (LCC) are used to allocate and control the
logic functions created in the logic array. Each LCC has four
primary inputs and three outputs. The inputs to each LCC are
complete sum-of-product logic functions from the array, which
can be used to implement combinatorial and sequential logic
functions, and to control LCC registers and I/O cell output
enables.
From Global Cell
System Clock
Preset RegT ype Reset
To
Global
Cells
From
Logic
Control
Cells
(LCC)
A
From
B
Array
C
D
125 Product
Term s
MUX
On/Off
P
D,T,J
Q
REG
K
R
MUX
MUX
To
Array
To
I/O
C ell
To
Logic Control
Cells
(LCC)
PA7572 Logic Array
100 Sum Terms
08-15-003A
Figure 3. PA7572 Logic Array
True Product-Term Sharing
The PEEL™ logic array provides several advantages over
common PLD logic arrays. First, it allows for true product-
term sharing, not simply product-term steering, as com-
monly found in other CPLDs. Product term sharing ensures
that product-terms are used where they are needed and
not left unutilized or duplicated. Secondly, the sum-of-
08-15-004A
Figure 4. Logic Control Cell Block Diagram
As shown in Figure 4, the LCC is made up of three signal
routing multiplexers and a versatile register with synchronous
or asynchronous D, T, or JK registers (clocked-SR registers,
which are a subset of JK, are also possible). See Figure 5.
EEPROM memory cells are used for programming the
desired configuration. Four sum-of-product logic functions
(SUM terms A, B, C and D) are fed into each LCC from the
logic array. Each SUM term can be selectively used for
multiple functions as listed below.
Anachip Corp.
www.anachip.com.tw
Rev. 1.0 Dec 16, 2004
2/10
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