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CAT1163 Datasheet PDF : 12 Pages
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CAT1163
READ OPERATIONS
The READ operation for the CAT1163 is initiated in the
same manner as the write operation with one exception, that
R/W bit is set to one. Three different READ operations are
possible: Immediate/Current Address READ,
Selective/Random READ and Sequential READ.
Immediate/Current Address Read
The CAT1163’s address counter contains the address of
the last byte accessed, incremented by one. In other words,
if the last READ or WRITE access was to address N, the
READ immediately following would access data from
address N+1. If N = E (where = 2047 for the CAT1163) then
the counter will ‘wrap around’ to address 0 and continue to
clock out data. After the CAT1163 receives its slave address
information (with the R/W bit set to one), it issues an
acknowledge, then transmits the 8−bit byte requested. The
master device does not send an acknowledge, but will
generate a STOP condition.
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Figure 9. Immediate Address Read Timing
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte addresses of the location it wishes to read.
After the CAT1163 acknowledges, the Master device sends
the START condition and the slave address again, this time
with the R/W bit set to one. The CAT1163 then responds
with its acknowledge and sends the 8−bit byte requested.
The master device does not send an acknowledge but will
generate a STOP condition.
Sequential Read
The Sequential READ operation can be initiated by either
the Immediate Address READ or Selective READ
operations. After the CAT1163 sends the inital 8−bit byte
requested, the Master will responds with an acknowledge
which tells the device it requires more data. The CAT1163
will continue to output an 8−bit byte for each acknowledge,
thus sending the STOP condition.
The data being transmitted from the CAT1163 is outputted
sequentially with data from address N followed by data from
address N+1. The READ operation address counter
increments all of the CAT1163 address bits so that the entire
memory array can be read during one operation. If more than
E (where E=2047 for the CAT1163) bytes are read out, the
counter will ‘wrap around’ and continue to clock out data
bytes.
Manual Reset Operation
The CAT116x RESET or RESET pin can also be used as
a manual reset input.
Only the “active” edge of the manual reset input is
internally sensed. The positive edge is sensed if RESET is
used as a manual reset input and the negative edge is sensed
if RESET is used as a manual reset input.
An internal counter starts a 200 ms count. During this
time, the complementary reset output will be kept in the
active state. If the manual reset input is forced active for
more than 200 ms, the complementary reset output will
switch back to the non active state after the 200 ms expired,
regardless for how long the manual reset input is forced
active.
The embedded EEPROM is disabled as long as a reset
condition is maintained on any RESET pin. If the external
forced RESET/RESET is longer than internal controlled
time−out period, tPURST, the memory will not respond with
an acknowledge for any access as long as the manual reset
input is active.
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