CAT1163 Ver la hoja de datos (PDF) - Catalyst Semiconductor => Onsemi

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CAT1163

Supervisory Circuit with I2C Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer

Catalyst Semiconductor => Onsemi 

CAT1163

FUNCTIONAL DESCRIPTION

The CAT1163 supports the I2C Bus data transmission

protocol. This Inter-Integrated Circuit Bus protocol defines

any device that sends data to the bus to be a transmitter

and any device receiving data to be a receiver. The

transfer is controlled by the Master device which

generates the serial clock and all START and STOP

conditions for bus access. Both the Master device and

Slave device can operate as either transmitter or receiver,

but the Master device controls which mode is activated.

I2C Bus Protocol

The features of the I2C bus protocol are defined as

follows:

(1) Data transfer may be initiated only when the bus is

not busy.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any changes in

the data line while the clock line is high will be interpreted

as a START or STOP condition.

START Condition

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of

SDA when SCL is HIGH. The CAT1163 monitors the

SDA and SCL lines and will not respond until this

condition is met.

Figure 5. Acknowledge Timing

SCL FROM

1

MASTER

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must end

with a STOP condition.

DEVICE ADDRESSING

The Master begins a transmission by sending a START

condition. The Master sends the address of the particular

slave device it is requesting. The four most significant

bits of the 8-bit slave address are fixed as 1010.

The next three bits (Figure 6) define memory addressing.

For the CAT1163 the three bits define higher order bits.

The last bit of the slave address specifies whether a

Read or Write operation is to be performed. When this bit

is set to 1, a Read operation is selected, and when set

to 0, a Write operation is selected.

After the Master sends a START condition and the slave

address byte, the CAT1163 monitors the bus and

responds with an acknowledge (on the SDA line) when

its address matches the transmitted slave address. The

CAT1163 then performs a Read or Write operation

depending on the R/W bit.

8

9

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

START

Figure 6. Slave Address Bits

ACKNOWLEDGE

CA24TC1116633 1 0 1 0 a10 a9 a8 R/W

* ‘X’ corresponds to Don’t Care Bits (can be zero or a one).

** a8, a9 and a10 correspond to the address of the memory array address word.

7

Doc No. 3003, Rev. C

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