CAT1163 Ver la hoja de datos (PDF) - Catalyst Semiconductor => Onsemi
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Fabricante
CAT1163
Catalyst Semiconductor => Onsemi
CAT1163 Datasheet PDF : 12 Pages
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CAT1163
CAPACITANCE
TA = 25˚C, f = 1.0 MHz, VCC = 5V
Symbol Test
CI/O(1)
Input/Output Capacitance (SDA)
CIN(1)
Input Capacitance (SCL)
AC CHARACTERISTICS
VCC=2.7V to 6.0V unless otherwise specified.
Output Load is 1 TTL Gate and 100pF.
SYMBOL PARAMETER
FSCL
TI(1)
Clock Frequency
Noise Suppresion Time
Constant at SCL, SDA Inputs
tAA
tBUF(1)
SLC Low to SDA Data Out
and ACK Out
Time the Bus Must be Free Before
a New Transmission Can Start
tHD:STA Start Condition Hold Time
tLOW
Clock Low Period
tHIGH
tSU:STA
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
tHD:DAT Data in Hold Time
tSU:DAT
tR(1)
tF(1)
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
tSU:STO Stop Condition Setup Time
tDH
Data Out Hold Time
Max
8
6
Units
pF
pF
Conditions
VI/O = 0V
VIN = 0V
VCC = 2.7V - 6V
Min
Max
100
200
3.5
4.7
4
4.7
4
4.7
0
50
1
300
4
100
VCC = 4.5V - 5.5V
Min
Max
400
200
1
1.2
0.6
1.2
0.6
0.6
0
50
0.3
300
0.6
100
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
POWER-UP TIMING (1)(2)
Symbol Parameter
tPUR
Power-up to Read Operation
tPUW
Power-up to Write Operation
Max
Units
1
ms
1
ms
WRITE CYCLE LIMITS
Symbol Parameter
Min
Typ
Max
Units
tWR
Write Cycle Time
10
ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specific operation can be initiated.
3
Doc No. 3003, Rev. C
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