SC16IS760 Ver la hoja de datos (PDF) - NXP Semiconductors.
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Fabricante
SC16IS760
NXP Semiconductors.
SC16IS760 Datasheet PDF : 63 Pages
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NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
Table 2. Pin description …continued
Symbol Pin
Type Description
TSSOP16 TSSOP24 HVQFN24
CS/A0
2
9
6
I
SPI chip select or I2C-bus device address select A0. If SPI
configuration is selected by I2C/SPI pin, this pin is the SPI chip
select pin (Schmitt-trigger, active LOW). If I2C-bus configuration is
selected by I2C/SPI pin, this pin along with A1 pin allows user to
change the device’s base address.
SI/A1
3
10
7
I
SPI data input pin or I2C-bus device address select A1. If SPI
configuration is selected by I2C/SPI pin, this is the SPI data input
pin. If I2C-bus configuration is selected by I2C/SPI pin, this pin
along with A0 pin allows user to change the device’s base address.
To select the device address, please refer to Table 32.
SO
4
11
8
O SPI data output pin. If SPI configuration is selected by I2C/SPI pin,
this is a 3-stateable output pin. If I2C-bus configuration is selected
by I2C/SPI pin, this pin function is undefined and must be left as
n.c. (not connected).
SCL/SCLK 5
12
9
I
I2C-bus or SPI input clock.
SDA
6
IRQ
7
GPIO0
-
13
10
I/O I2C-bus data input/output, open-drain if I2C-bus configuration is
selected by I2C/SPI pin. If SPI configuration is selected then this
pin is an undefined pin and must be connected to VSS.
14
11
O Interrupt (open-drain, active LOW). Interrupt is enabled when
interrupt sources are enabled in the Interrupt Enable Register
(IER). Interrupt conditions include: change of state of the input
pins, receiver errors, available receiver buffer data, available
transmit buffer space, or when a modem status flag is detected. An
external resistor (1 k for 3.3 V, 1.5 k for 2.5 V) must be
connected between this pin and VDD.
15
12
I/O programmable I/O pin[2]
GPIO1
-
16
13
I/O programmable I/O pin[2]
GPIO2
-
17
14
I/O programmable I/O pin[2]
GPIO3
-
18
15
I/O programmable I/O pin[2]
GPIO4/DSR -
20
17
I/O programmable I/O pin or modem’s DSR pin[2][3]
GPIO5/DTR -
21
18
I/O programmable I/O pin or modem’s DTR pin[2][3]
GPIO6/CD -
22
19
I/O programmable I/O pin or modem’s CD pin[2][3]
GPIO7/RI -
23
20
I/O programmable I/O pin or modem’s RI pin[2][3]
RTS
10
24
21
O UART request to send (active LOW). A logic 0 on the RTS pin
indicates the transmitter has data ready and waiting to send.
Writing a logic 1 in the modem control register MCR[1] will set this
pin to a logic 0, indicating data is available. After a reset this pin is
set to a logic 1. This pin only affects the transmit and receive
operations when auto RTS function is enabled via the Enhanced
Feature Register (EFR[6]) for hardware flow control operation.
VSS
9
VSS
-
19
16[4]
-
ground
-
center
-
The center pad on the back side of the HVQFN24 package is
pad[4]
metallic and should be connected to ground on the printed-circuit
board.
[1] See Section 7.4.1 “Hardware reset, Power-On Reset (POR) and software reset”
[2] These pins have an active pull-up resistor at their inputs. See Table 36.
[3] Selectable with IOControl register bit 1.
SC16IS740_750_760
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 9 June 2011
© NXP B.V. 2011. All rights reserved.
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