SC16IS760IPW Ver la hoja de datos (PDF) - NXP Semiconductors.

Número de pieza

componentes Descripción

Fabricante

SC16IS760IPW

Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support

NXP Semiconductors. 

NXP Semiconductors

SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

UART 1

RX

FIFO

SERIAL TO

RX

PARALLEL

FLOW

CONTROL

RTS

UART 2

TX

PARALLEL

TO SERIAL

CTS

FLOW

CONTROL

TX

FIFO

TX

FIFO

PARALLEL

TX

TO SERIAL

FLOW

CONTROL

CTS

RX

SERIAL TO

PARALLEL

RTS

FLOW

CONTROL

Fig 8. Autoflow control (auto RTS and auto CTS) example

RX

FIFO

002aab656

7.2.1 Auto RTS

Figure 9 shows RTS functional timing. The receiver FIFO trigger levels used in auto RTS

are stored in the TCR or FCR. RTS is active if the RX FIFO level is below the halt trigger

level in TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTS is deasserted.

The sending device (for example, another UART) may send an additional character after

the trigger level is reached (assuming the sending UART has another character to send)

because it may not recognize the deassertion of RTS until it has begun sending the

additional character. RTS is automatically reasserted once the receiver FIFO reaches the

resume trigger level programmed via TCR[7:4]. This reassertion allows the sending

device to resume transmission.

RX

start

character

N

stop

start

character

N+1

stop

start

RTS

receive

FIFO

read

1

2

N

N+1

002aab040

(1) N = receiver FIFO trigger level.

(2) The two blocks in dashed lines cover the case where an additional character is sent, as described in Section 7.2.1

Fig 9. RTS functional timing

SC16IS740_750_760

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7 — 9 June 2011

© NXP B.V. 2011. All rights reserved.

10 of 63

Share Link: