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PTN3392 Datasheet PDF : 32 Pages
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NXP Semiconductors
PTN3392
2-lane DisplayPort to VGA adapter IC
7.3 DPCD registers
DPCD registers that are part of the VESA DisplayPort v1.1a are described in detail in
Ref. 1. The following paragraphs only describe the specific implementation by PTN3392.
The PTN3392 DisplayPort receiver capability and status information about the link are
reported by DisplayPort Configuration Data (DPCD) registers, when a DisplayPort source
issues a read command on the AUX CH. The DisplayPort source device can also write to
the link configuration field of DPCD to configure and initialize the link. The DPCD is
DisplayPort v1.1a compliant.
It is the responsibility of the host to only issue commands within the capability of the
PTN3392 as defined in the ‘Receiver Capability Field’ in order to prevent undefined
behavior. PTN3392 specific DPCD registers are listed in Table 4.
7.3.1 PTN3392 specific DPCD register settings
Table 4. PTN3392 specific DPCD registers
DPCD
Description
register [1]
Receiver Capability Field
0000Bh
RECEIVE_PORT1_CAP_1. ReceiverPort1 Capability_1.
0000Ch
I2C-bus speed control capabilities bit map. The bit values in this register are
assigned to I2C-bus speeds as follows:
Bits 7:0
0000 0001b = 1 kbit/s; supported by PTN3392
0000 0010b = 3 kbit/s; supported by PTN3392
0000 0100b = 10 kbit/s; supported by PTN3392
0000 1000b = 100 kbit/s; supported by PTN3392
0001 0000b = 400 kbit/s; not supported by PTN3392
0010 0000b = 1 Mbit/s; not supported by PTN3392
0100 0000b = reserved
1000 0000b = 50 kbit/s; supported by PTN3392BS/F3
1000 0000b = reserved in PTN3392BS/F1, PTN3392BS/F2
Power-on Read/write
Reset value over AUX CH
00h
read only
8Fh
read only
PTN3392
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 5 June 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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