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PTN3392

2-lane DisplayPort to VGA adapter IC

NXP Semiconductors. 

NXP Semiconductors

PTN3392

2-lane DisplayPort to VGA adapter IC

Table 3. Pin description …continued

Symbol

Pin

Type

Strap pins, S[3:0]

S0

33

input

S1

34

input

S2

35

input

S3

36

Miscellaneous

RESET_N

1

input

input

CLK_O

2

LDOCAP_CORE 30

OSC_IN

26

OSC_OUT

27

LDOCAP_AUX 38

RRX

42

output

power

input

output

power

input

Description

Open (internal pull-down) = logic 0:

Implement VGA-side monitor detect

according to VESA DisplayPort Standard

v1.1a sections 7 and 8 (Ref. 1). Refer to

Section 7.4.1 for S0 = 0 behavior.

HIGH (external pull-up) = logic 1:

Set HPD HIGH upon VGA monitor

detection; set HPD LOW upon VGA monitor

detachment. Refer to Section 7.4.2 for

S0 = 1 behavior.

Default S0 = 0 for standard compliance.

reserved; leave open-circuit (default internal

pull-down)

Open (internal pull-down) = logic 0 to set

default I2C speed to 50 kbit/s for

PTN3392BS/F3, 100 kbit/s for

PTN3392BS/F1, PTN3392BS/F2.

HIGH (external pull-up) = logic 1, to set

default I2C speed to 10 kbit/s.

This pin may be left open-circuit (internal

pull-down) or tied to VDD according to the

desired default I2C speed. See more

explanation in Table 4 about S2 pin setting

and DPCD register 00109h.

reserved; leave open-circuit (default internal

pull-down)

Hardware reset input (active LOW); internal

pull-up. A capacitor must be connected

between this pin and ground. A 1 F capacitor

is recommended.

DisplayPort receiver test clock output

1.8 V digital core supply decoupling

crystal oscillator input

crystal oscillator output

1.8 V AUX supply decoupling

Receiver termination resistance control. A

12 k resistor must be connected between

this pin and LDOCAP_AUX (pin 38).

[1] HVQFN48 package die supply ground is connected to both GND pins and exposed center pad. GND pins

7, 23, 28, 29, 41, 45, 48, and exposed center pad must be connected to supply ground for proper device

operation. For enhanced thermal, electrical, and board level performance, the exposed pad must be

soldered to the board using a corresponding thermal pad on the board and for proper heat conduction

through the board, thermal vias must be incorporated in the PCB in the thermal pad region.

PTN3392

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 5 — 5 June 2014

© NXP Semiconductors N.V. 2014. All rights reserved.

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