PTN3392 Ver la hoja de datos (PDF) - NXP Semiconductors.
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componentes Descripción
Fabricante
PTN3392 Datasheet PDF : 32 Pages
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NXP Semiconductors
PTN3392
2-lane DisplayPort to VGA adapter IC
Table 3. Pin description …continued
Symbol
Pin
Type
DisplayPort
ML0_P
43
self-biasing
differential input
ML0_N
44
self-biasing
differential input
ML1_P
46
self-biasing
differential input
ML1_N
47
self-biasing
differential input
AUX_P
39
self-biasing
differential
input/output
AUX_N
40
self-biasing
differential
input/output
HPD
3
3.3 V TTL
single-ended output
RGB DAC outputs
BLU
16
analog output
BLU_N
19
analog output
GRN
21
analog output
GRN_N
20
analog output
RED
25
analog output
RED_N
24
analog output
RSET
22
analog input/output
DDC
SCL
11
SDA
13
Monitor-side sync
HSYNC
15
VSYNC
14
JTAG
TCK
5
TDO
6
TMS
8
TRST_N
9
TDI
10
single-ended 5 V
open-drain DDC I/O
single-ended 5 V
open-drain DDC I/O
single-ended 3.3 V
TTL output
single-ended 3.3 V
TTL output
input
output
input
input
input
Description
DisplayPort main lane signal lane 0, positive
DisplayPort main lane signal lane 0, negative
DisplayPort main lane signal lane 1, positive
DisplayPort main lane signal lane 1, negative
DisplayPort auxiliary channel signal, positive
DisplayPort auxiliary channel signal, negative
Hot-plug detect
‘blue’ current analog output
‘blue’ current complementary analog output
‘green’ current analog output
‘green’ current complementary analog output
‘red’ current analog output
‘red’ current complementary analog output
DAC full-scale current control resistor.
Pull down to ground by an external
1.2 k 1 % resistor.
5 V sink-side DDC clock I/O. Pulled up by
1.2 k external resistor to 5 V.
5 V sink-side DDC data I/O. Pulled up by
1.2 k external resistor to 5 V.
horizontal sync signal to monitor; serial
resistance of 36 is recommended.
vertical sync signal to monitor; serial
resistance of 36 is recommended.
JTAG clock input
JTAG data output
JTAG mode select input
JTAG reset (active LOW) input
JTAG data input
PTN3392
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 5 June 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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