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PTN3392

2-lane DisplayPort to VGA adapter IC

NXP Semiconductors. 

NXP Semiconductors

PTN3392

2-lane DisplayPort to VGA adapter IC

2.3 Analog video output

 VSIS 1.2 compliance (Ref. 3) for all supported video output modes

 Analog RGB current-source outputs

 VSYNC and HSYNC outputs

 Pixel clock up to 240 MHz

 Triple 8-bit Digital-to-Analog Converter (DAC)

 Direct drive of double terminated 75  load with standard 700 mV (peak-to-peak)

signals

2.4 General features

 Supports ‘Flash-over-AUX’ field upgradability

 Monitor presence detection. Connection/disconnection reported via HPD IRQ and

DPCD update.

 All display resolutions from VGA to WUXGA are supported1, including e.g.:

 WUXGA: 6 bits, 1920  1200, 60 Hz, 193 MHz pixel clock rate

 WUXGA: 1920  1200, 60 Hz, reduced blanking, 154 MHz pixel clock rate

 UXGA: 1600  1200, 60 Hz, 162 MHz pixel clock rate

 SXGA: 1280  1024, 60 Hz, 108 MHz pixel clock rate

 XGA: 1024  768, 60 Hz, 65 MHz pixel clock rate

 SVGA: 800  600, 60 Hz, 40 MHz pixel clock rate

 VGA: 640  480, 60 Hz, 25 MHz pixel clock rate

 Any resolution and refresh rates are supported up to 8 bit color

 Bits per color (bpc) supported1

 6, 8 bits supported

 10, 12, 16 bits supported by truncation to 8 MSBs

 All VGA colorimetry formats (RGB) supported

 Power modes

 Active-mode power consumption:

~600 mW at UXGA / 162 MHz pixel clock

~500 mW at SXGA / 108 MHz pixel clock

 ~40 mW at Low-power mode or before link training started

 On-board crystal oscillator for use with external 27 MHz crystal

 ESD protection

 7 kV ESD HBM JEDEC

 8 kV ESD HBM IEC 61000-4-2 (Ref. 4)

 3.3 V  10 % power supply

 Commercial temperature range: 0 C to 85 C

 48-pin HVQFN, 7 mm  7 mm  0.85 mm (nominal); 0.5 mm pitch; lead-free package

1. Except for color depth beyond 8 bits, display resolutions and refresh rates are only limited to those which a standard 2-lane

DisplayPort configuration is able to support.

PTN3392

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 5 — 5 June 2014

© NXP Semiconductors N.V. 2014. All rights reserved.

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