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TRW Datasheet PDF : 59 Pages
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NOTE
The total number of bits in a ShockBurstTM RF package may not exceed 256!
Maximum length of payload section is hence given by:
DATAx_W(bits)=256-ADDR_W-CRC
Where:
ADDR_W: length of RX address set in configuration word B[23:18]
CRC: check sum, 8 or 16 bits set in configuration word B[17]
PRE: preamble, 4 or 8 bits are automatically included
Shorter address and CRC leaves more room for payload data in each package.
ADDRx
ADDR2
103 102 101 ….. 71 70 69 68 67 66 65 64
ADDR1
63
62
61 ….. 31
30
29
28
27
26
25
24
Table 5 Address of receiver #2 and receiver #1
Bit 103-64:
ADDR2: Receiver address channel 2, up to 40 bit.
Bit 63-24:
ADDR1: Receiver address channel 1, up to 40 bit.
NOTE
Bits in ADDRx exceeding the address width set in ADDR_W are redundant and can be
set to logic 0.
ADDR_W & CRC
ADDR_W
CRC_L CRC_EN
23
22
21
20
19
18
17
16
Table 6 Number of bits reserved for RX address + CRC setting
Bit 23-18:
ADDR_W: Number of bits reserved for RX address in ShockBurstTM packages.
NOTE
Maximum number of address bits is 40 (5 bytes). Values over 40 in A DDR_W are not
valid.
Bit 17:
Bit 16:
CRC_L: CRC length to be calculated by TRW-24G in shockBurst.
Logic 0: 8 bit CRC
Logic 1: 16 bit CRC
CRC_EN: Enables on-chip CRC generation (TX) and verification (RX).
Logic 0: On-chip CRC generation/checking disabled
Logic 1: On-chip CRC generation/checking enabled
NOTE
An 8 bit CRC will increase the number of payload bits possible in each S hockBurstTM
data packet, but will also reduce the system integrity.
http://www.wenshing.com.tw ; http://www.rf.net.tw
TRW-24G Datasheet P.11
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