6N138 Ver la hoja de datos (PDF) - Fairchild Semiconductor
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6N138 Datasheet PDF : 15 Pages
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Isolation Characteristics (TA = 0 to 70°C unless otherwise specified)
Symbol
Characteristics
Test Conditions
Min.
II-O
VISO
RI-O
CI-O
II-I
RI-I
CI-I
Input-output
insulation leakage current
(Note 4)
Withstand insulation test voltage
(Note 4)
Resistance (input to output)
(Note 4)
Capacitance (input to output)
(Note 4, 5)
Input-Input
Insulation leakage current
(Note 6)
Input-Input Resistance
(Note 6)
Input-Input Capacitance
(Note 6)
(Relative humidity = 45%)
(TA = 25°C, t = 5 s)
(VI-O = 3000VDC)
(RH ≤ 50%, TA = 25°C, II-O ≤ 2µA)
( t = 1 min.)
(VI-O = 500VDC)
2500
(f = 1MHz)
(RH ≤ 45%, VI-I = 500VDC)
t = 5 s, (HCPL2730/2731 only)
(VI-I = 500VDC)
(HCPL2730/2731 only)
(f = 1 MHz)
(HCPL2730/2731 only)
** All Typicals at TA = 25°C
Typ.* Max.
1.0
1012
0.6
0.005
1011
0.03
Unit
µA
VRMS
Ω
pF
µA
Ω
pF
Notes:
1. Current Transfer Ratio is defined as a ratio of output collector current, IO, to the forward LED input current, IF, times 100%.
2. Pin 7 open. (6N138 and 6N139 only)
3. Common mode transient immunity in logic HIGH level is the maximum tolerable (positive) dVcm/dt on the leading edge of
the common mode pulse signal VCM, to assure that the output will remain in a logic HIGH state (i.e., VO > 2.0V). Common
mode transient immunity in logic LOW level is the maximum tolerable (negative) dVcm/dt on the trailing edge of the
common mode pulse signal, VCM, to assure that the output will remain in a logic LOW state (i.e., VO < 0.8V).
4. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted
together.
5. For dual channel devices, CI-O is measured by shorting pins 1 and 2 or pins 3 and 4 together and pins 5 through 8 shor ted
together.
6. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together.
I
©2005 Fairchild Semiconductor Corporation
6N138, 5N139, NCPL2730, HCPL2731 Rev. 1.0.3
5
www.fairchildsemi.com
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