AT90PWM81(2010) Ver la hoja de datos (PDF) - Atmel Corporation

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AT90PWM81
(Rev.:2010)

8-bit Microcontroller with 8K Bytes In-System Programmable Flash

Atmel Corporation 

3. AVR CPU Core

3.1 Introduction

This section discusses the AVR core architecture in general. The main function of the CPU core is to

ensure correct program execution. The CPU must therefore be able to access memories, perform calcula-

tions, control peripherals, and handle interrupts.

3.2 Architectural Overview

Figure 3-1. Block Diagram of the AVR Architecture

Data Bus 8-bit

Flash

Program

Memory

Instruction

Register

Instruction

Decoder

Control Lines

Program

Counter

Status

and Control

32 x 8

General

Purpose

Registrers

ALU

Interrupt

Unit

SPI

Unit

Watchdog

Timer

Analog

Comparator

Data

SRAM

EEPROM

I/O Module1

I/O Module 2

I/O Module n

I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate

memories and buses for program and data. Instructions in the program memory are executed with a single

level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the pro-

gram memory. This concept enables instructions to be executed in every clock cycle. The program

memory is In-System Reprogrammable Flash memory.

8 AT90PWM81

7734P–AVR–08/10

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