ADV7626 Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
ADV7626 Datasheet PDF : 24 Pages
| |||
Data Sheet
ADV7626
Parameter
Symbol Test Conditions/Comments Min
Typ
Max
Unit
EP_SCLK High Time
t24
45
55
% duty
cycle
EP_SCLK Low Time
45
55
% duty
cycle
EP_MOSI Setup Time
t25
0.5
ns
EP_MOSI Hold Time
t26
1.4
ns
EP_SCLK Falling Edge to EP_MISO t27
5.5
ns
Start of Data Invalid
EP_SCLK Falling Edge to EP_MISO t28
End of Data Invalid
9
ns
AUDIO INPUT PORTS, I2S INPUT
APx_IN_SCLK High Time
t37
45
55
% duty
cycle
APx_IN_SCLK Low Time
45
55
% duty
cycle
APx_IN Data Setup Time
t38
2.3
ns
APx_IN Data Hold Time
t39
1.6
ns
AUDIO INPUT PORTS, DSD INPUT
APx_IN_SCLK High Time
t40
45
55
% duty
cycle
APx_IN_SCLK Low Time
45
55
% duty
cycle
APx_IN DSD Data Setup Time
t41
2.3
ns
APx_IN DSD Data Hold Time
t42
1.6
ns
AUDIO OUTPUT PORTS, I2S OUTPUT
APx_OUT_SCLK High Time
t46
45
55
% duty
cycle
APx_OUT_SCLK Low Time
45
55
% duty
cycle
APx_OUT LRCLK Transition Time
t47
Start of invalid LRCLK to falling
APx_OUT_SCLK edge
10
ns
APx_OUT LRCLK Transition Time
t48
Falling APx_OUT_SCLK edge
to end of invalid LRCLK
10
ns
APx_OUT Data Transition Time
t49
Start of invalid data to falling
APx_OUT_SCLK edge
10
ns
APx_OUT Data Transition Time
t50
Falling APx_OUT_SCLK edge
to end of invalid data
10
ns
AUDIO OUTPUT PORTS, DSD OUTPUT
APx_OUT_SCLK High Time
t51
45
55
% duty
cycle
APx_OUT_SCLK Low Time
45
55
% duty
cycle
APx_OUT DSD Data Transition Time t52
Start of invalid data to falling
APx_OUT_SCLK edge
10
ns
APx_OUT DSD Data Transition Time t53
Falling APx_OUT_SCLK edge
to end of invalid data
10
ns
1 xCL refers to SCL, DDC_SCL_RXA, and DDC_SCL_RXB.
2 xDA refers to SDA, DDC_SDA_RXA, and DDC_SDA_RXB.
3 SPI Mode 0 only.
4 All serial port measurements are for CPHA = 0, CPOL = 0 (clock is low in idle state; negative edge of clock is used to transmit data and positive edge is used to sample data).
5 Measurements guaranteed by design only.
Rev. 0 | Page 7 of 24
Share Link: 