LE82Q35SLJA7 Ver la hoja de datos (PDF) - Intel

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LE82Q35SLJA7

Intel® 3 Series Express Chipset Family

Intel 

8.2.16

8.2.17

8.2.18

8.2.19

8.2.20

8.2.21

8.2.22

8.2.23

8.2.24

8.2.25

8.2.26

8.2.27

MAXLAT—Maximum Latency ................................................... 276

CAPID0—Mirror of Dev0 Capability Identifier ............................. 276

MGGC—Mirror of Dev 0 GMCH Graphics Control Register ............. 277

DEVEN—Device Enable........................................................... 279

SSRW—Mirror of Fun 0 Software Scratch Read Write .................. 281

BSM—Mirror of Func0 Base of Stolen Memory............................ 281

HSRW—Mirror of Dev2 Func0 Hardware Scratch Read Write ........ 282

GDRST—Mirror of Dev2 Func0 Graphics Reset ........................... 282

PMCAPID—Mirror of Fun 0 Power Management Capabilities ID...... 283

PMCAP—Mirror of Fun 0 Power Management Capabilities ............. 284

PMCS—Power Management Control/Status ................................ 285

SWSMI—Mirror of Func0 Software SMI ..................................... 286

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Intel® Management Engine (ME) Subsystem Registers (D3:F0,F1,F2,F3) ............... 288

9.1 Host Embedded Controller Interface (HECI1) Configuration Register

Details (D3:F0) .................................................................................. 288

9.1.1 ID— Identifiers ..................................................................... 289

9.1.2 CMD— Command .................................................................. 290

9.1.3 STS— Device Status .............................................................. 291

9.1.4 RID— Revision ID.................................................................. 292

9.1.5 CC— Class Code.................................................................... 292

9.1.6 CLS— Cache Line Size............................................................ 292

9.1.7 MLT— Master Latency Timer ................................................... 293

9.1.8 HTYPE— Header Type ............................................................ 293

9.1.9 HECI_MBAR— HECI MMIO Base Address ................................... 294

9.1.10 SS— Sub System Identifiers ................................................... 294

9.1.11 CAP— Capabilities Pointer....................................................... 295

9.1.12 INTR— Interrupt Information .................................................. 295

9.1.13 MGNT— Minimum Grant ......................................................... 295

9.1.14 MLAT— Maximum Latency ...................................................... 296

9.1.15 HFS— Host Firmware Status ................................................... 296

9.1.16 PID— PCI Power Management Capability ID .............................. 296

9.1.17 PC— PCI Power Management Capabilities.................................. 297

9.1.18 PMCS— PCI Power Management Control And Status ................... 298

9.1.19 MID— Message Signaled Interrupt Identifiers ............................ 299

9.1.20 MC— Message Signaled Interrupt Message Control ..................... 299

9.1.21 MA— Message Signaled Interrupt Message Address .................... 300

9.1.22 MUA— Message Signaled Interrupt Upper Address (Optional)....... 300

9.1.23 MD— Message Signaled Interrupt Message Data ........................ 301

9.1.24 HIDM—HECI Interrupt Delivery Mode ....................................... 301

9.2 HECI2 Configuration Register Details (D3:F1) (Intel® 82Q35 and

82Q33 GMCH only) ............................................................................. 302

9.2.1 ID— Identifiers ..................................................................... 303

9.2.2 CMD— Command .................................................................. 303

9.2.3 STS— Device Status .............................................................. 305

9.2.4 RID— Revision ID.................................................................. 306

9.2.5 CC— Class Code.................................................................... 306

9.2.6 CLS— Cache Line Size............................................................ 306

9.2.7 MLT— Master Latency Timer ................................................... 307

9.2.8 HTYPE— Header Type ............................................................ 307

9.2.9 HECI_MBAR— HECI MMIO Base Address ................................... 308

9.2.10 SS— Sub System Identifiers ................................................... 308

9.2.11 CAP— Capabilities Pointer....................................................... 309

9.2.12 INTR— Interrupt Information .................................................. 309

9.2.13 MGNT— Minimum Grant ......................................................... 309

Datasheet

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