9.2.14 MLATâ Maximum Latency ...................................................... 310
9.2.15 HFSâ Host Firmware Status ................................................... 310
9.2.16 PIDâ PCI Power Management Capability ID .............................. 310
9.2.17 PCâ PCI Power Management Capabilities.................................. 311
9.2.18 PMCSâ PCI Power Management Control And Status ................... 312
9.2.19 MIDâ Message Signaled Interrupt Identifiers ............................ 313
9.2.20 MCâ Message Signaled Interrupt Message Control ..................... 313
9.2.21 MAâ Message Signaled Interrupt Message Address .................... 314
9.2.22 MUAâ Message Signaled Interrupt Upper Address (Optional)....... 314
9.2.23 MDâ Message Signaled Interrupt Message Data ........................ 315
9.2.24 HIDMâHECI Interrupt Delivery Mode ....................................... 315
9.3 IDE Function for Remote Boot and Installations PT IDER Register
Details (D3:F2) (IntelÂź 82Q35 and 82Q33 GMCH Only) ............................ 316
9.3.1 IDâIdentification .................................................................. 317
9.3.2 CMDâCommand Register ....................................................... 317
9.3.3 STSâDevice Status ............................................................... 319
9.3.4 RIDâRevision ID................................................................... 320
9.3.5 CCâClass Codes ................................................................... 320
9.3.6 CLSâCache Line Size............................................................. 320
9.3.7 MLTâMaster Latency Timer .................................................... 321
9.3.8 HTYPEâHeader Type ............................................................. 321
9.3.9 PCMDBAâPrimary Command Block IO Bar ................................ 322
9.3.10 PCTLBAâPrimary Control Block Base Address............................ 322
9.3.11 SCMDBAâSecondary Command Block Base Address................... 323
9.3.12 SCTLBAâSecondary Control Block base Address ........................ 323
9.3.13 LBARâLegacy Bus Master Base Address ................................... 324
9.3.14 SSâSub System Identifiers .................................................... 325
9.3.15 EROMâExpansion ROM Base Address....................................... 325
9.3.16 CAPâCapabilities Pointer........................................................ 326
9.3.17 INTRâInterrupt Information ................................................... 326
9.3.18 MGNTâMinimum Grant .......................................................... 327
9.3.19 MLATâMaximum Latency ....................................................... 327
9.3.20 PIDâPCI Power Management Capability ID ............................... 327
9.3.21 PCâPCI Power Management Capabilities................................... 328
9.3.22 PMCSâPCI Power Management Control and Status .................... 328
9.3.23 MIDâMessage Signaled Interrupt Capability ID ......................... 330
9.3.24 MCâMessage Signaled Interrupt Message Control ...................... 330
9.3.25 MAâMessage Signaled Interrupt Message Address ..................... 331
9.3.26 MAUâMessage Signaled Interrupt Message Upper Address .......... 331
9.3.27 MDâMessage Signaled Interrupt Message Data ......................... 332
9.4 Serial Port for Remote Keyboard and Text KT Redirection Register
Details (D3:F3) (IntelÂź 82Q35 and 82Q33 GMCH Only) ............................ 333
9.4.1 IDâIdentification .................................................................. 334
9.4.2 CMDâCommand Register ....................................................... 334
9.4.3 STSâDevice Status ............................................................... 336
9.4.4 RIDâRevision ID................................................................... 337
9.4.5 CCâClass Codes ................................................................... 337
9.4.6 CLSâCache Line Size............................................................. 337
9.4.7 MLTâMaster Latency Timer .................................................... 338
9.4.8 HTYPEâHeader Type ............................................................. 338
9.4.9 KTIBAâKT IO Block Base Address............................................ 339
9.4.10 KTMBAâKT Memory Block Base Address................................... 339
9.4.11 SSâSub System Identifiers .................................................... 340
9.4.12 EROMâExpansion ROM Base Address....................................... 341
9.4.13 CAPâCapabilities Pointer........................................................ 341
10
Datasheet