HEF4017B Ver la hoja de datos (PDF) - NXP Semiconductors.

Número de pieza

componentes Descripción

Fabricante

HEF4017B

5-stage Johnson decade counter

NXP Semiconductors. 

NXP Semiconductors

HEF4017B

5-stage Johnson decade counter

VDD

VI

G

VO

DUT

RT

CL

001aag182

Test data is given in Table 10.

Definitions for test circuit:

DUT = Device Under Test;

CL = load capacitance including jig and probe capacitance;

RT = termination resistance should be equal to the output impedance Zo of the pulse generator.

Fig 10. Test circuit

Table 10. Test data

Supply voltage

VDD

5 V to 15 V

Input

VI

VSS or VDD

13. Application information

tr, tf

≤ 20 ns

Load

CL

50 pF

Some examples of applications for the HEF4017B are:

• Decade counter with decimal decoding

• 1 out of n decoding counter (when cascaded)

• Sequential controller

• Timer

Figure 11 shows a technique for extending the number of decoded output states for the

HEF4017B. Decoded outputs are sequential within each stage and from stage to stage,

with no dead time (except propagation delay).

CP0 MR

HEF4017B

CP1

Q0 Q1- - - - Q8 Q9

CP0 MR

HEF4017B

CP1

Q0 Q1- - - - Q8 Q9

CP0 MR

HEF4017B

CP1

Q1 - - - - - - Q8 Q9

9 decoded

outputs

8 decoded

outputs

8 decoded

outputs

clock

first stage

intermediate stages

last stage

001aae577

Enabling the counter on CP1 when CP0 is HIGH, or on CP0 when CP1 is LOW, causes an extra count.

Fig 11. Counter expansion

HEF4017B_4

Product data sheet

Rev. 04 — 9 December 2008

© NXP B.V. 2008. All rights reserved.

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