KSZ8895RQTR Ver la hoja de datos (PDF) - Micrel

Número de pieza

componentes Descripción

Fabricante

KSZ8895RQTR

Ethernet Switch w/ MII/RMII Eval

Micrel 

Micrel, Inc.

KSZ8895MQ/RQ/FMQ

List of Figures

Figure 1. Broadband Gateway ..................................................................................................................................... 13

Figure 2. Integrated Broadband Router ....................................................................................................................... 13

Figure 3. Standalone Switch ........................................................................................................................................ 14

Figure 4. Using KSZ8895FMQ for Dual Media Converter ........................................................................................... 14

Figure 5. KSZ8895MQ/RQ/FMQ 128-Pin PQFP Pins Configuration ........................................................................... 15

Figure 6. Typical Straight Cable Connection ............................................................................................................... 28

Figure 7. Typical Crossover Cable Connection ........................................................................................................... 29

Figure 8. Auto-Negotiation ........................................................................................................................................... 30

Figure 9. Destination Address Lookup Flow Chart, Stage 1 ........................................................................................ 35

Figure 10. Destination Address Resolution Flow Chart, Stage 2.................................................................................. 36

Figure 11. 802.1p Priority Field Format......................................................................................................................... 42

Figure 12. Tail Tag Frame Format ............................................................................................................................... 45

Figure 13. KSZ8895MQ/RQ/FMQ EEPROM Configuration Timing Diagram .............................................................. 49

Figure 14. SPI Write Data Cycle .................................................................................................................................. 50

Figure 15. SPI Read Data Cycle .................................................................................................................................. 50

Figure 16. SPI Multiple Write ....................................................................................................................................... 51

Figure 17. SPI Multiple Read ....................................................................................................................................... 51

Figure 18. EEPROM Interface Input Receive Timing Diagram.................................................................................. 106

Figure 19. EEPROM Interface Output Transmit Timing Diagram .............................................................................. 106

Figure 20. SNI Input Timing ....................................................................................................................................... 107

Figure 21. SNI Output Timing .................................................................................................................................... 107

Figure 22. MAC Mode MII Timing – Data Received from MII .................................................................................... 108

Figure 23. MAC Mode MII Timing – Data Transmitted from MII ................................................................................ 108

Figure 24. PHY Mode MII Timing – Data Received from MII..................................................................................... 109

Figure 25. PHY Mode MII Timing – Data Transmitted from MII................................................................................. 109

Figure 26. RMII Timing – Data Received from RMII .................................................................................................. 110

Figure 27. RMII Timing – Data Transmitted to RMII .................................................................................................. 110

Figure 28. SPI Input Timing ....................................................................................................................................... 111

Figure 29. SPI Output Timing..................................................................................................................................... 112

Figure 30. Auto-Negotiation Timing ........................................................................................................................... 113

Figure 31. MDC/MDIO Timing.................................................................................................................................... 114

Figure 32. Reset Timing ............................................................................................................................................. 115

Figure 33. Recommended Reset Circuit .................................................................................................................... 116

Figure 34. Recommended Circuit for Interfacing with CPU/FPGA Reset.................................................................. 116

March 12, 2014

11

Revision 1.7

Share Link: