KSZ8895MQX-EVAL Ver la hoja de datos (PDF) - Micrel

Número de pieza

componentes Descripción

Fabricante

KSZ8895MQX-EVAL

Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII Interface

Micrel 

KSZ8895MQX/RQX/FQX/ML

Integrated 5-Port 10/100 Managed Ethernet

Switch with MII/RMII Interface

Revision 1.1

General Description

The KSZ8895MQX/RQX/FQX/ML is a highly-integrated,

Layer 2 managed, five-port switch with numerous features

designed to reduce system cost. Intended for cost-

sensitive 10/100Mbps five-port switch systems with low

power consumption, on-chip termination, and internal core

power controllers, it supports high-performance memory

bandwidth and shared memory-based switch fabric with

non-blocking configuration. Its extensive feature set

includes power management, programmable rate limit and

priority ratio, tag/port-based VLAN, packets filtering, four-

queue QoS prioritization, management interfaces, and MIB

counters. The KSZ8895 family provides multiple CPU data

interfaces to effectively address both current and emerging

fast Ethernet applications when port 5 is configured to

separate MAC5 with SW5-MII/RMII and PHY5 with P5-

MII/RMII interfaces.

The KSZ8895 family offers three configurations, providing

the flexibility to meet different requirements:

 KSZ8895MQX/ML: 5 10/100Base-T/TX transceivers,

1 SW5-MII and 1 P5-MII interface

 KSZ8895RQX: 5 10/100Base-T/TX transceivers, 1

SW5-RMII and 1 P5-RMII interface

 KSZ8895FQX: 4 10/100Base-T/TX transceivers on

Ports 1, 2, 3 and 5 (port 3 can be set to the fiber

mode). 1 100Base-FX transceivers on Port 4. 1 SW5-

MII and 1 P5-MII interface

All registers of MACs and PHYs units can be managed by

the SPI or the SMI interface. MIIM registers can be

accessed through the MDC/MDIO interface. EEPROM can

set all control registers for the unmanaged mode.

KSZ8895MQX/RQX/FQX are 128-pin PQFP package.

KSZ8895ML is 128-pin LQFP package.

Datasheets and support documentation are available on

Micrel’s web site at: www.micrel.com.

Functional Diagram

Auto MDI/MDIX

Auto MDI/MDIX

Auto MDI/MDIX

Auto MDI/MDIX

Auto MDI/MDIX

P5-MII/RMII

MDC/MDIO for MIIM and SMI

SW5-MII/RMII or SNI

Control Reg SPI I/F

LED0[5:1]

LED1[5:1]

LED2[5:1]

KSZ8895MQX/RQX/FQX/ML

10/100

T/TX

PHY1

10/100

T/TX

PHY2

10/100

T/TX/FX

PHY3

10/100

T/TX/FX

PHY4

10/100

T/TX

PHY5

10/100

MAC 1

10/100

MAC 2

10/100

MAC 3

10/100

MAC 4

10/100

MAC 5

LED I/F

SPI

Control

Registers

Look Up

Engine

Queue

Management

Buffer

Management

Frame

Buffers

MIB

Counters

EEPROM

Interface

Note: SW5 indicates the MAC5 of the switch side, P5 indicates the PHY5 of the Port 5.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

April 28, 2014

Revision-1.1

Share Link: