KSZ8895MQX-EVAL Ver la hoja de datos (PDF) - Micrel
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KSZ8895MQX-EVAL Datasheet PDF : 128 Pages
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Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
Register 237 (0xED): Port 4 Queue 2 Egress Limit Control 3 ............................................................................... 98
Register 253 (0xFD): Port 5 Queue 2 Egress Limit Control 3 ............................................................................... 98
Data Rate Limit Selection Limit Table ....................................................................................................................... 99
Register 191(0xBF): Testing Register 1 ................................................................................................................ 99
Register 207(0xCF): Reserved Control Register .................................................................................................. 99
Register 223(0xDF): Testing Register 2 ................................................................................................................ 99
Register 239(0xEF): Port 3 Copper or Fiber Control ............................................................................................. 99
Register 255(0xFF): Testing Register 3................................................................................................................. 99
Static MAC Address Table .......................................................................................................................................... 100
Format of Static MAC Table for Reads (32 entries) ................................................................................................ 100
Format of Static MAC Table for Writes (32 entries) ................................................................................................ 100
Dynamic MAC Address Table ..................................................................................................................................... 104
Format of Dynamic MAC Address Table (1K entries) ............................................................................................. 104
MIB (Management Information Base) Counters ......................................................................................................... 106
For Port 1 ............................................................................................................................................................. 106
For port 2, the base is 0x20, same offset definition (0x20-0x3f).......................................................................... 107
For port 3, the base is 0x40, same offset definition (0x40-0x5f).......................................................................... 107
For port 4, the base is 0x60, same offset definition (0x60-0x7f).......................................................................... 107
For port 5, the base is 0x80, same offset definition (0x80-0x9f).......................................................................... 107
Format of Per Port MIB Counters (16 entries)......................................................................................................... 107
Format of All Port Dropped Packet MIB Counters................................................................................................... 107
MIIM Registers ............................................................................................................................................................ 109
Register 0h: MII Control........................................................................................................................................... 109
Register 1h: MII Status ............................................................................................................................................ 110
Register 2h: PHYID HIGH ....................................................................................................................................... 110
Register 3h: PHYID LOW ........................................................................................................................................ 110
Register 4h: Advertisement Ability........................................................................................................................... 110
Register 5h: Link Partner Ability .............................................................................................................................. 111
Register 1dh: LinkMD Control/Status ..................................................................................................................... 111
Register 1fh: PHY Special Control/Status ............................................................................................................... 112
Absolute Maximum Ratings(1)...................................................................................................................................... 113
Operating Ratings(2) .................................................................................................................................................... 113
Electrical Characteristics(4,5) ........................................................................................................................................ 113
Timing Diagrams ......................................................................................................................................................... 115
EEPROM Timing ..................................................................................................................................................... 115
SNI Timing ............................................................................................................................................................... 116
MII Timing ................................................................................................................................................................ 117
SPI Timing ............................................................................................................................................................... 120
Auto-Negotiation Timing .......................................................................................................................................... 122
MDC/MDIO Timing .................................................................................................................................................. 123
Reset Timing............................................................................................................................................................ 124
Reset Circuit Diagram.............................................................................................................................................. 125
April 28, 2014
11
Revision-1.1
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