74F374 Ver la hoja de datos (PDF) - NXP Semiconductors.

Número de pieza

componentes Descripción

Fabricante

74F374

74F373 Octal transparent latch (3-State) 74F374 Octal D flip-flop (3-State)

NXP Semiconductors. 

Philips Semiconductors

Latch/flip-flop

Product data

74F373/74F374

AC SET-UP REQUIREMENTS

SYMBOL

PARAMETER

tsu (H)

tsu (L)

th (H)

th (L)

tw (H)

tsu (H)

tsu (L)

th (H)

th (L)

tw (H)

tw (L)

Set-up time, HIGH or LOW level

Dn to E

Hold time, HIGH or LOW level

Dn to E

E Pulse width, HIGH

Set-up time, HIGH or LOW level

Dn to CP

Hold time, HIGH or LOW level

Dn to CP

CP Pulse width,

HIGH or LOW

74F373

74F374

TEST

CONDITION

Waveform 4

Waveform 4

Waveform 1

Waveform 5

Waveform 5

Waveform 5

LIMITS

Tamb = +25 °C

VCC = +5.0 V

CL = 50 pF, RL = 500 Ω

MIN TYP MAX

Tamb = 0 °C to +70 °C

VCC = +5.0 V ± 10%

CL = 50 pF, RL = 500 Ω

MIN

MAX

0

0

1.0

1.0

3.0

3.0

3.0

3.0

3.5

4.0

2.0

2.0

2.0

2.0

0

0

0

0

3.5

3.5

4.0

4.0

UNIT

ns

ns

ns

ns

ns

ns

AC WAVEFORMS

For all waveforms, VM = 1.5 V.

The shaded areas indicate when the input is permitted to change for

predictable output performance.

CP VM

1/fmax

tw(H)

tPLH

VM

tw(L)

VM

tPHL

Qn

VM

VM

SF00258

Waveform 1. Propagation delay for clock input to output,

clock pulse widths, and maximum clock frequency

tw(H)

E VM

VM

tPHL

Qn

VM

VM

tPLH

VM

SF00259

Waveform 2. Propagation delay for enable to output

and enable pulse width

Dn VM

tPLH

VM

tPHL

Qn

VM

VM

SF00260

Waveform 3. Propagation delay for data to output

Dn

VM

VM

tsu(H) th(H)

E

VM

VM

tsu(L)

VM

th(L)

VM

SF00261

Waveform 4. Data set-up time and hold times

2002 Nov 20

7

Share Link: