AD5737 Ver la hoja de datos (PDF) - Analog Devices
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AD5737 Datasheet PDF : 44 Pages
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AD5737
Data Sheet
AC PERFORMANCE CHARACTERISTICS
AVDD = VBOOST_x = 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V;
REFIN = 5 V; RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
DYNAMIC PERFORMANCE, CURRENT
OUTPUT
Output Current Settling Time
Output Noise (0.1 Hz to 10 Hz
Bandwidth)
Output Noise Spectral Density
Min
Typ
Max
Unit
Test Conditions/Comments
15
µs
See Test Conditions/Comments ms
0.15
LSB p-p
0.5
nA/√Hz
To 0.1% FSR, 0 mA to 24 mA range
For settling times when using the dc-to-dc con-
verter, see Figure 25, Figure 26, and Figure 27
12-bit LSB, 0 mA to 24 mA range
Measured at 10 kHz, midscale output, 0 mA
to 24 mA range
1 Guaranteed by design and characterization; not production tested.
TIMING CHARACTERISTICS
AVDD = VBOOST_x = 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V;
REFIN = 5 V; RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1, 2, 3
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t194
Limit at TMIN, TMAX
33
13
13
13
13
198
5
5
20
5
10
500
See Table 2
10
5
40
21
5
500
800
20
5
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
µs min
µs min
ns min
ns max
µs max
ns min
µs max
ns max
µs min
µs min
ns min
ns min
µs min
µs min
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24th/32nd SCLK falling edge to SYNC rising edge (see Figure 53)
SYNC high time
Data setup time
Data hold time
SYNC rising edge to LDAC falling edge (all DACs updated or any channel has
digital slew rate control enabled)
SYNC rising edge to LDAC falling edge (single DAC updated)
LDAC pulse width low
LDAC falling edge to DAC output response time
DAC output settling time
CLEAR high time
CLEAR activation time
SCLK rising edge to SDO valid
SYNC rising edge to DAC output response time (LDAC = 0)
All DACs updated
Single DAC updated
LDAC falling edge to SYNC rising edge
RESET pulse width
SYNC high to next SYNC low (digital slew rate control enabled)
All DACs updated
Single DAC updated
1 Guaranteed by design and characterization; not production tested.
2 All input signals are specified with tRISE = tFALL = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.
3 See Figure 3, Figure 4, Figure 5, and Figure 6.
4 This specification applies if LDAC is held low during the write cycle; otherwise, see t9.
Rev. B | Page 6 of 44
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