SI4362 Ver la hoja de datos (PDF) - Silicon Laboratories

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SI4362

HIGH-PERFORMANCE, LOW-CURRENT RECEIVER

Silicon Laboratories 

Si4362

3.2. Fast Response Registers

The fast response registers are registers that can be read immediately without the requirement to monitor and

check CTS. There are four fast response registers that can be programmed for a specific function. The fast

response registers can be read through API commands, 0x50 for Fast Response A, 0x51 for Fast Response B,

0x53 for Fast Response C, and 0x57 for Fast Response D. The fast response registers can be configured by the

“FRR_CTL_X_MODE” properties.

The fast response registers may be read in a burst fashion. After the initial 16 clock cycles, each additional eight

clock cycles will clock out the contents of the next fast response register in a circular fashion. The value of the

FRRs will not be updated unless NSEL is toggled.

3.3. Operating Modes and Timing

The primary states of the Si4362 are shown in Figure 5. The shutdown state completely shuts down the radio to

minimize current consumption. Standby/Sleep, SPI Active, Ready, and RX tune are available to optimize the

current consumption and response time to RX for a given application. API commands START_RX, and

CHANGE_STATE control the operating state with the exception of shutdown which is controlled by SDN, pin 1.

Table 10 shows each of the operating modes with the time required to reach RX mode as well as the current

consumption of each mode. The times in Table 9 are measured from the rising edge of nSEL until the chip is in the

desired state. Note that these times are indicative of state transition timing but are not guaranteed and should only

be used as a reference data point. An automatic sequencer will put the chip into RX from any state. It is not

necessary to manually step through the states. To simplify the diagram it is not shown but any of the lower power

states can be returned to automatically after RX.

Shutdown

SPI Active

Sleep

Ready

Rx Tune

Rx

Figure 5. State Machine Diagram

Rev 0.4

15

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