ADM705ARZ(2016) Ver la hoja de datos (PDF) - Analog Devices
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ADM705ARZ Datasheet PDF : 8 Pages
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ADM705/ADM706/ADM707/ADM708
CIRCUIT INFORMATION
POWER FAIL RESET OUTPUT
RESET is an active low output that provides a reset signal to
the microprocessor whenever the VCC input is below the reset
threshold. An internal timer holds RESET low for 200 ms after
the voltage on VCC rises above the threshold. This functions as a
power-on reset signal for the microprocessor. It allows time for
both the power supply and the microprocessor to stabilize after
power-up. The RESET output is guaranteed to remain valid (low)
with VCC as low as 1 V. This ensures that the microprocessor is
held in a stable shutdown condition as the power supply voltage
ramps up.
In addition to RESET, an active high RESET output is also available
on the ADM707/ADM708. This is the complement of RESET
and is useful for processors requiring an active high reset signal.
MANUAL RESET
The manual reset input (MR) allows other reset sources, such as
a manual reset switch, to generate a processor reset. The input is
effectively debounced by the timeout period (200 ms typically).
The MR input is TTL-/CMOS-compatible, so it can also be driven
by any logic reset output.
VCC
VRT
VRT
tRS
tRS
RESET
MR
MR EXTERNALLY
DRIVEN LOW
WDO
Figure 13. RESET, MR, and WDO Timing
WATCHDOG TIMER (ADM705/ADM706)
The watchdog timer circuit can monitor the activity of the micro-
processor to check that it is not stalled in an indefinite loop. An
output line on the processor toggles the watchdog input (WDI)
line. If this line is not toggled within the timeout period (1.60 sec),
then the watchdog output (WDO) goes low. The WDO can be
connected to a nonmaskable interrupt (NMI) on the processor;
therefore, if the watchdog timer times out, an interrupt is gen-
erated. The interrupt service routine then rectifies the problem.
If a RESET signal is required when a timeout occurs, the WDO
must connect to the manual reset input (MR).
Data Sheet
The watchdog timer is cleared by either a high to low or a low to
high transition on WDI. It is also cleared by RESET going low;
therefore, the watchdog timeout period begins after RESET
goes high.
When VCC falls below the reset threshold, WDO is forced low,
whether or not the watchdog timer has timed out. Normally, this
generates an interrupt, but it is overridden by RESET going low.
The watchdog monitor can be deactivated by floating the WDI.
The WDO can then be used as a low line output because it goes
low only when VCC falls below the reset threshold.
tWP
tWD
tWD
tWD
WDI
WDO
RESET
RESET EXTERNALLY
TRIGGERED BY MR
tRS
Figure 14. Watchdog Timing
POWER FAIL COMPARATOR
The power fail comparator is an independent comparator that
can monitor the input power supply. The comparator inverting
input is internally connected to a 1.25 V reference voltage. The
noninverting input is available at the PFI input. This input can
monitor the input power supply via a resistive divider network.
When the voltage on the PFI input drops below 1.25 V, the
comparator output (PFO) goes low, indicating a power failure. For
early warning of power failure, the comparator monitors the
preregulator input by choosing an appropriate resistive divider
network. The PFO output can interrupt the processor so a
shutdown procedure is implemented before power is lost.
As the voltage on the PFI pin is limited to VCC + 0.3 V, it is
recommended to connect the PFI pin with a Schottky diode to
the RESET pin as shown in Figure 15. This helps clamping the
PFI pin voltage during device power up and operation.
INPUT
POWER
R1
1.25V
PFO
POWER-FAIL PFI
R2
INPUT
RESET
ADM705/ADM706/
ADM707/ADM708
POWER-FAIL
OUTPUT
RESET
OUTPUT
Figure 15. Power Fail Comparator
Rev. H | Page 8 of 12
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