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74ALVT16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

Nexperia B.V. All rights reserved 

Nexperia

74ALVT16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

VI

input nDn,

nCE

GND

VM

VM

tsu(H) th(H)

VM

VM

tsu(L) th(L)

VI

input nCP

VM

VM

GND

001aad 401

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Figure 6. Data set-up and hold times

VI

input nMR

VM

VM

GND

VI

t WL

t rec

input nCP

VM

GND

VOH

t PHL

output nQn

VM

VOL

001aad 400

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Figure 7. Master reset pulse width, master reset to output delay and master reset to clock recovery time

VI

nOE input

VM

VM

GND

VCC

nQn output

LOW-to-OFF

OFF-to-LOW

VOL

VOH

nQn output

HIGH-to-OFF

OFF-to-HIGH

GND

tPLZ

tPZL

tPHZ

VX

VY

outputs

enabled

VM

tPZH

VM

outputs

disabled

outputs

enabled

001aal795

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Figure 8. OFF-state to HIGH and LOW propagation delays and LOW and HIGH to OFF-state propagation delays

74ALVT16823

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 5 — 22 January 2018

© Nexperia B.V. 2018. All rights reserved.

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