V961PBC Ver la hoja de datos (PDF) - QuickLogic Corporation
Número de pieza
componentes Descripción
Fabricante
V961PBC Datasheet PDF : 16 Pages
| |||
V961PBC
Table 3: Signal Descriptions
Signal
Type Ra
PCI Bus Interface
Description
AD[31:0] PCI I/O Z Address and data, multiplexed on the same pins.
C/BE[3:0] PCI I/O Z Bus Command and Byte Enables, multiplexed on the same pins.
PAR
PCI I/O Z Parity represents even parity across AD[31:0] and C/BE[3:0].
FRAME
PCI I/O
Z
Cycle Frame indicates the beginning and burst length of an
access.
IRDY
PCI I/O
Z
Initiator Ready indicates the initiating agent’s (bus master’s) ability
to complete the current data phase of the transaction.
TRDY
PCI I/O
Z
Target Ready indicates the target agent’s (selected device’s) abil-
ity to complete the current data phase of the transaction.
STOP
PCI I/O
Z
Stop indicates the current target is requesting the master to stop
the current transaction (retry or disconnect).
DEVSEL
PCI I/O
Device Select, when actively driven by a target, indicates the driv-
Z
ing device has decoded its address as the target of the current
access. As an input to the initiator, DEVSEL indicates whether
any device on the bus has been selected.
IDSEL
PCI I
Initialization Device Select is used as a chip select during configu-
ration read and write transactions. It must be driven high in order
to access the chip’s internal configuration space.
REQ
PCI O
H
Request indicates to the arbiter that this agent requests use of the
bus.
GNT
PCI I
Grant indicates to the agent that access to the bus has been
granted.
PCLK
PCI I
PCLK provides timing for all transactions on the PCI bus.
PRST
PCI I/O
Acts as an input when RDIR is high, an output when RDIR is low.
Z/L As an input it is asserted low to bring all internal PBC operation to
a reset state.
PERR
PCI I/O
Z
Parity Error is used to report data parity errors during all PCI
transactions except a Special Cycle.
SERR
PCI I/OD
System Error is used to report address parity errors, data parity
Z errors on the Special Cycle command, or any other system error
where the result will be catastrophic.
INT[A:D] PCI I/OD Z Level-sensitive interrupt requests may be received or generated.
Copyright © 1998, V3 Semiconductor Inc.
V961PBC Data Sheet Rev 2.4
3
Share Link: 