V961PBC Ver la hoja de datos (PDF) - QuickLogic Corporation

Número de pieza

componentes Descripción

Fabricante

V961PBC

LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS

QuickLogic Corporation 

V961PBC Rev. B2

LOCAL BUS TO PCI BRIDGE

FOR MULTIPLEXED A/D PROCESSORS

• Glueless interface between Intel i960Jx, IBM

PPC401Gx, processors and PCI bus

• Fully compliant with PCI 2.1 specification

• Configurable for primary master, bus master, or

target operation

• Up to 1Kbyte burst access support on both local

and PCI interface

• 576 bytes of programmable FIFO storage with

DYNAMIC BANDWIDTH ALLOCATION™

• Two channel DMA controller

• Enhanced support for 8/16-bit local bus devices

with programmable region size register

• 16 8-bit bi-directional mailbox registers with

doorbell interrupts

• Dual bi-directional address space remapping

• On-the-fly byte order (endian) conversion

• Optional power on serial EEPROM initialization

• I2O ATU and messaging unit including

hardware controlled circular queues

• Flexible PCI and local interrupt management

• Support for real-mode DOS "holes"

• Ability to generate both Type 0 and Type 1

configuration cycles

• 33MHz and 40MHz local bus versions available

with independent PCI operation up to 33MHz

• Low cost 160-pin EIAJ PQFP package

V961PBC provides the highest performance,

most flexible, and most economical method to

directly connect i960Jx or PPC401Gx processors

to the PCI bus. V961PBC is also a suitable

candidate for a variety of 32-bit multiplexed local

bus applications based on Motorola, IBM, Intel

embedded processors - where a minimal amount

of glue logic is required. V961PBC may also be

used in systems without a CPU for a generic PCI

master/target interface.

V961PBC Rev B2 is the first I2O ready PCI

bridge, fully backward compatible with V292PBC

Rev B1. The PCI bus can be run at the full

33MHz frequency, independent of local bus

clock rate. The overall throughput of the system

is dramatically improved by increasing the FIFO

depth and utilizing the unique DYNAMIC

BANDWIDTH ALLOCATION™ architecture.

Access to the PCI bus can be performed through

two programmable address apertures. Two more

apertures are provided for PCI-to-local bus

accesses. There are 32-bytes of read FIFO’s in

each direction, 16-byte dedicated for each

aperture. V961PBC also includes bi-directional

remapping capabilities, and on-the-fly byte order

conversion

Two DMA channels are provided for autonomous

PCI-to-Local/Local-to-PCI transfers. Mailbox

registers and flexible PCI interrupt controllers are

also included to provide a simple mechanism to

emulate PCI device control ports.

The part is available in 160-pin low cost EIAJ

Plastic Quad Flat Pack (PQFP) package.

i960Jx

PPC401Gx

CPU

V96BMC

D

MEMORY

R

CONTROL

A

M

ROM

TYPICAL APPLICATION

V961PBC

LOCAL TO

PCI BRIDGE

PCI

PERIPHERAL

PCI SLOT or EDGE CONNECTOR

Copyright © 1998, V3 Semiconductor Inc.

V961PBC Data Sheet Rev 2.4

1

V3 Semiconductor reserves the right to change the specifications of this product without notice.

V961PBC, V96SSC and V96BMC are trademarks of V3 Semiconductor. All other trademarks are the property of their respective owners.

Share Link: