V962PBC Ver la hoja de datos (PDF) - QuickLogic Corporation

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componentes Descripción

Fabricante

V962PBC

LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS

QuickLogic Corporation 

V962PBC

Signal

LD[31:0]

LA[31:2]

BE[3:0]

W/R

ADS

READY

HOLD

HOLDA

LPAR[3:0]

BLAST

BTERM

LINT

LRST

LCLK

Table 3: Signal Descriptions (cont’d)

Type

I/O4

I/O4

I/O4

I/O4

I/O4

I/O4

O4

I

I/O4

I/O4

I/O4

O4

I/O4

I

Local Bus Interface

R Description

Z Local multiplexed address and data bus.

Z Local address bus.

Z Local bus byte enables.

Z Write/Read.

Z Asserted low to indicate the beginning of a bus cycle.

Z Local Bus data ready

L

Local bus hold request: asserted by the chip to initiate a local bus

master cycle.

Local bus hold acknowledge.

Z Local bus parity.

Z Burst request. Burst last.

Z Bus Time-out. Burst terminate.

H Local interrupt request.

L/Z Local bus RESET signal.

Local bus clock.

Signal

SCL/LPERR

SDA

Type

O4

I/O4

Serial EEPROM Interface

R Description

X EEPROM clock. Local parity error.

X EEPROM data.

Signal

RDIR

Type

I

Configuration

R Description

Reset direction. Tie low to drive PRST out and LRST in, high to

drive LRST out and PRST in.

4

V962PBC Data Sheet Rev 2.4

Copyright © 1998, V3 Semiconductor Inc.

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