High-Bandwidth, Quad DPDT Switches
Timing Circuits/Timing Diagrams
MAX4760
MAX4761
VN_
NO_
OR NC_
LOGIC
INPUT
IN_
GND
V+
V+
COM_
RL
VOUT
CL
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
( ) VOUT = VN_
RL
RL + RON
Figure 2. Switching Time
V+
LOGIC
INPUT 0V
50%
tr < 5ns
tf < 5ns
50%
SWITCH 0V
OUTPUT
tOFF
VOUT 0.9 x V0UT
0.9 x VOUT
tON
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
MAX4760
MAX4761
VN_
LOGIC
INPUT
V+
V+
NC_
COM_
NO_
IN_
GND
VOUT
RL
CL
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
Figure 3. Break-Before-Make Interval
V+
LOGIC
INPUT
50%
0V
VOUT
0.9 x VOUT
tBBM
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