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NCP5425DBR2G

Dual Synchronous Buck Controller

ON Semiconductor 

NCP5425

APPLICATIONS INFORMATION

Theory of Operation

The NCP5425 is a very versatile buck controller using

V2t control method. It can be configured as:

• Dual output Buck Controller.

• Two phase Buck Controller with current limit.

• Two phase Buck Controller with input power ratio and

current limit.

The fixed−frequency architecture, driven from a common

oscillator, ensures a 180° phase differential between

channels.

V2 Control Method

The V2 method of control uses a ramp signal generated by

the ESR (Effective Series Resistance) of the output

capacitors. This ramp is proportional to the AC current

through the main inductor and is offset by the DC output

voltage. This control scheme inherently compensates for

variation in either line or load conditions, since the ramp

signal is generated from the output voltage itself. The V2

method differs from traditional techniques such as voltage

mode control, which generates an artificial ramp, and

current mode control, which generates a ramp using the

inductor current.

−PWM

+

GATE(H)

GATE(L)

RAMP

COMP

Slope

Compensation

Error Signal

Error

Amplifier

−

+

Output

Voltage

VFB

Reference

Voltage

Figure 3. V2 Control with Slope Compensation

The V2 control method is illustrated in Figure 3. The

output voltage generates both the error signal and the ramp

signal. Since the ramp signal is simply the output voltage, it

is affected by any change in the output, regardless of the

origin of that change. The ramp signal also contains the DC

portion of the output voltage, allowing the control circuit to

drive the main switch to 0% or 100% duty cycle as required.

A variation in line voltage changes the current ramp in the

inductor, which causes the V2 control scheme to compensate

the duty cycle. Since any variation in inductor current

modifies the ramp signal, as in current mode control, the V2

control scheme offers the same advantages in line transient

response. A variation in load current will affect the output

voltage, modifying the ramp signal. A load step immediately

changes the state of the comparator output, which controls

the main switch. The comparator response time and the

transition speed of the main switch determine the load

transient response. Unlike traditional control methods, the

reaction time to the output load step is not related to the

crossover frequency of the error signal loop. The error signal

loop can have a low crossover frequency, since the transient

response is handled by the ramp signal loop. The main

purpose of this ‘slow’ feedback loop is to provide DC

accuracy. Noise immunity is significantly improved, since

the error amplifier bandwidth can be rolled off at a low

frequency. Enhanced noise immunity improves remote

sensing of the output voltage, since the noise associated with

long feedback traces can be effectively filtered. Line and

load regulation are drastically improved because there are

two independent control loops. A voltage mode controller

relies on the change in the error signal to compensate for a

deviation in either line or load voltage. This change in the

error signal causes the output voltage to change

corresponding to the gain of the error amplifier, the

consequence of which is normally specified as line or load

regulation. A current mode controller maintains a fixed error

signal during line transients, since the slope of the ramp

signal changes in this case. However, regulation of load

transients still requires a change in the error signal. The V2

method of control maintains a fixed error signal for both line

and load variation, since the ramp signal is affected by both

line and load.

The stringent load transient requirements of modern

power supplies require the output capacitors to have very

low ESR. The resulting shallow slope in the output ripple

can lead to pulse width jitter and variation caused by both

random and synchronous noise. A ramp waveform

generated in the oscillator is added to the ramp signal from

the output voltage to provide the proper voltage ramp at the

beginning of each switching cycle. This slope compensation

increases the noise immunity, particularly at higher duty

cycle (above 50%).

Startup

The NCP5425 features a programmable soft−start

function, which is implemented through the error amplifier

and external compensation capacitor. This feature reduces

stress to the power components and limits overshoot of the

output voltage, during startup. As power is applied to the

regulator, the NCP5425 Undervoltage Lockout circuit

(UVLO) monitors the IC’s supply voltage (VCC). The

UVLO circuit prevents the MOSFET gates from switching

until VCC exceeds 4.2 V. Internal UVLO threshold

hysteresis of 200 mV improves noise immunity. During

startup, the external Compensation Capacitor connected to

the COMP pin is charged by an internal 30 mA current

source. When the capacitor voltage exceeds the 0.3 V offset

of the PWM comparator, the PWM control loop will allow

switching to occur. The upper gate driver GATE(H) is now

activated, turning on the upper MOSFET. The output current

then ramps up through the main inductor and linearly

powers the output capacitors and load. When the regulator

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