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M66307FP

LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS

MITSUBISHI ELECTRIC  

MITSUBISHI 〈DIGITAL ASSP〉

M66307SP/FP

LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS

PIN DESCRIPTIONS

Pin

Name

I/O

Function

D0~D15 Data inputs

Input Normally connected to a 16-bit bus.

WR

Write control Input Data or command is stored to the M66307 at the Low to High transition. This signal is normally

input

connected to the write control signal of the control bus.

CS

Chip select

Input When Low, this signal allows data or command to be stored from the MPU to the M66307. It is normally

input

connected to the address bus directly or via a decoder. When this signal is High, the MPU cannot

access the M66307.

DACK

DMA

acknowledge

input

Input

When Low, this signal allows data to be stored by DMA transfer. It is normally connected to the DMA

acknowledge output (DACK) of the DMA controller.For systems where DMA transfer is not used, this

pin must be pulled-up to VCC.

C/D

Command/

Input This signal discriminates whether the information on the data bus when the MPU accessed the M66307

data control

is command or data. When High, the signal indicates that the information is a command; when Low, it

input

indicates data. It is normally connected to the address bus directly or via a decoder.

RESET Reset input

Input

When Low, this signal initializes the command registers and various circuits of the M66307. As a result,

all active Low output signals are set High; clock outputs (CLK, φ OUT) are set High; data output (DATA

OUT) is set Low.

DREQ

DMA request

output

Output

This signal requests DMA cycles. When data store by DMA cycle is defined in the initialization and the

number of DMA transfer words is specified, this output is set Low when the M66307 is set into the write

mode.

When the set number of DMA cycles are completed, it returns High.

INTR

Interrupt

Output This signal requests an interrupt to the MPU when the written data is sent out (Low output). This

request output

request is cleared by MPU access or toggle input(TOG) [when extended toggle is used] (High output).

BUSY/

ORDY

BUSY/

OUTPUT

READY

output

Output

When Low, this signal informs the MPU that no commands other than STOP can be set to the M66307,

and informs the peripheral equipment that the M66307 is sending data.

When the M66307 is in the send mode, this signal is set Low; when transmission is completed, it

returns High.

CLKE

Clock enable Input When Low, this signal enables clock input (CLK/φ IN); when High, it disables the clock input. When

input

clock input is φ IN, CLKE is invalid so that this pin must be pulled-up to VCC or pulled-down to GND.

CLK/φ IN Clock input

Input

CLK IN is generally used as data request clock from peripheral equipment; φ IN is generally used as

continuous clock on the system side. Selection between CLK IN and φ IN is specified by the initialization

command. Select CLK IN when the data output timing must be matched to the timing of the peripheral

equipment. Select φ IN when the timing need not be matched and data can be sent at a stroke using the

clock from the system. φ IN can be divided into one of five smaller frequencies when the peripheral

equipment is slow to read data. (Note: The continuous clock of φ IN may not necessarily be the system

clock.)

TOG

Toggle input

Input

This signal can only be valid when extended toggle is used (using two M66307s) and CLK IN is

selected for clock input. This input sets the write and send modes. Each time this signal is set Low, the

IC in the write mode is reversed to the send mode and the IC in the send mode is reversed to the write

mode. It is impossible to control mode inversion with this function and operation mode setting

command together.

DATA

OUT

CLK/

φ OUT

EXD

Data output

Output The data stored in the internal memory or fixed data is serially output synchronously with clock input

(CLK/φ IN) according to the settings of output format (LSB/MSB, LIFO/FIFO).

Clock output

Extended D

input

Output Peripheral devices take in data with the “rise” of clock pulses.

Input

This signal is used for an extended system using two M66307s. Connect the EXD of the master IC to

the DATA OUT pin of the slave IC. The EXD of the slave IC must be pulled-up to VCC. (See the

application example.) For normal use, pull up EXD to VCC or pull down it to GND.

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