M66307FP Ver la hoja de datos (PDF) - MITSUBISHI ELECTRIC
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M66307FP Datasheet PDF : 22 Pages
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M66307SP/FP MIMTSITUSBUIBSHISIH〈DI 〈IDGIIGTAITLAALSASSPS〉P〉
M66307SP/FP
LINLEINSECASNCABNUFBFUEFRFEwRithw1it6h-B16ITBMITPMUPBUUBSUCSOCMOPMATPIABTLIBELIENPINUPTUSTS
DESCRIPTION
The M66307SP/FP is an integrated circuit consisting of a line buffer
with static memory, manufactured by the silicon gate CMOS pro-
cess, which satisfies A3-paper 400DPI requirements. It converts the
stored data from the 16-bit MPU bus into serial data and outputs it at
a transfer rate of up to 10Mbps synchronously with the external data
request clock or an arbitrary continuous clock.
FEATURES
• 16-bit MPU bus compatible
• Writing data via DMAC is possible
• 320-word (5,120-bit) static RAM
• Data output rate of up to 10Mbps
• Built-in function to add fixed data of a specified length at the be-
ginning of output data (Fixed data: Continuous High bit or Low bit
data)
• The output format can be selected between FIFO or LIFO.
• The output method can be selected from two:
(1) Synchronized with an arbitrary continuous clock (φ IN) on the
system side; the frequency of clock output (CLK/φ OUT) can
be divided by 1, 2, 4, 8, or 16.
(2) Synchronized with the data request clock (CLK IN) on the pe-
ripheral equipment side.
• Up to two devices can be cascaded.
(1) Toggle configuration
(2) 32-bit bus configuration
• High fan-out outputs (CLK/φ OUT, DATA OUT).
Io = ±24mA
(±4mA for INTR and DREQ
±8mA for BUSY/ORDY)
PIN CONFIGURATION (TOP VIEW)
D8
1
32 VCC(5V)
D9
2
31 D7
D10
3
30 D6
D11
4
DATA INPUTS
D12
5
D13
6
29 D5
28 D4
DATA INPUTS
27 D3
D14
7
26 D2
D15
8
25 D1
WRITE CONTROL
INPUT
WR
9
CHIP SELECT INPUT CS 10
COMMAND/DATA
CONTROL INPUT C/D 11
24 D0
DMA ACKNOWLEDGE
23 DACK
INPUT
22
DREQ
DMA REQUEST
OUTPUT
RESET INPUT RESET 12
21 EXD EXTENDED D INPUT
INTERROUUPTTPRUETQUESTINTR
13
20 TOG TOGGLE INPUT
CLOCK INPUT CLK/ φ IN 14
CLOCK ENABLE
INPUT
CLKE
15
19 CLK/ φ OUT CLOCK
OUTPUT
18 DATA OUT DATA OUTPUT
(0V)GND 16
17
BUSY/ORDY
BUSY/
OUTPUT
READY
Outline 32P4B
OUTPUT
32P2W-A
• The clock input (CLK/φ IN) contains a Schmitt trigger.
• The reset (RESET), Write (WR) and toggle input (TOG) contain
negative noise reduction circuits.
APPLICATION
Image-handling general OA equipment
BLOCK DIAGRAM
WR 9
CS 10
C/D 11
DACK 23
D0 24
D1 25
D2 26
D3 27
D4 28
D5 29
D6 30
D7 31
D8 1
D9 2 16
D10 3
D11 4
D12 5
D13 6
D14 7
D15 8
TOG 20
EXD 21
CLK/ φ IN 14
CLKE 15
Write
control
circuit
16
16
Command registers
Fixed data
length register
DREQ words register
Mode register
Expansion
control
circuit
GND VCC
16 32
Write/send 13
address
control
circuit
9
4
320 word
CMOS 16
SRAM
16
Clock
control
circuit
Frequency
divider
Clock signal
select circuit
RESET 12
Reset
control
circuit
9 Output
control
circuit
13
Output
control
circuit
Output
control
circuit
Output
control
circuit
22 DREQ
13 INTR
17 BUSY/ORDY
18 DATA OUT
19 CLK/ φ OUT
1
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