KSZ9021RL Ver la hoja de datos (PDF) - Micrel

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KSZ9021RL

Gigabit Ethernet Transceiver with RGMII Support

Micrel 

Micrel, Inc.

KSZ9021RL/RN

List of Tables

Table 1. MDI/MDI-X Pin Mapping ........................................................................................................................................ 25

Table 2. Auto-Negotiation Timers ........................................................................................................................................ 28

Table 3. RGMII Signal Definition.......................................................................................................................................... 29

Table 4. RGMII Pad Skew Registers ................................................................................................................................... 30

Table 5. Absolute Delay for 4-Bit Pad Skew Setting............................................................................................................ 31

Table 6. RGMII In-Band Status ............................................................................................................................................ 32

Table 7. MII Management Frame Format – for KSZ9021RL/RN ......................................................................................... 32

Table 8. Single LED Mode – Pin Definition .......................................................................................................................... 33

Table 9. Tri-color Dual LED Mode – Pin Definition .............................................................................................................. 33

Table 10. NAND Tree Test Pin Order – for KSZ9021RL ..................................................................................................... 34

Table 11. NAND Tree Test Pin Order – for KSZ9021RN .................................................................................................... 34

Table 12. RGMII v1.3 Specification (Timing Specifics from Table 2) .................................................................................. 50

Table 13. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters ............................................................................... 51

Table 14. MDC/MDIO Timing Parameters ........................................................................................................................... 52

Table 15. Reset Timing Parameters .................................................................................................................................... 53

Table 16. Reference Crystal/Clock Selection Criteria.......................................................................................................... 55

Table 17. Magnetics Selection Criteria ................................................................................................................................ 55

Table 18. Qualified Single Port 10/100/1000 Magnetics...................................................................................................... 55

February 13, 2014

7

Revision 1.2

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