CY7C1373D-133BZXI Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY7C1373D-133BZXI

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Architecture

Cypress Semiconductor 

PRELIMINARY

CY7C1371D

CY7C1373D

Pin Definitions

Name

A0, A1, A

BWA, BWB

BWC, BWD

WE

ADV/LD

I/O

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

CLK

Input-

Clock

CE1

Input-

Synchronous

CE2

Input-

Synchronous

CE3

Input-

Synchronous

OE

Input-

Asynchronous

CEN

ZZ

DQs

Input-

Synchronous

Input-

Asynchronous

I/O-

Synchronous

DQPX

MODE

VDD

VDDQ

VSS

TDO

I/O-

Synchronous

Input Strap Pin

Power Supply

I/O Power Supply

Ground

JTAG serial output

Synchronous

Description

Address Inputs used to select one of the address locations. Sampled at the

rising edge of the CLK. A[1:0] are fed to the two-bit burst counter.

Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.

Sampled on the rising edge of CLK.

Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is

active LOW. This signal must be asserted LOW to initiate a write sequence.

Advance/Load Input. Used to advance the on-chip address counter or load a new

address. When HIGH (and CEN is asserted LOW) the internal burst counter is

advanced. When LOW, a new address can be loaded into the device for an access.

After being deselected, ADV/LD should be driven LOW in order to load a new

address.

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified

with CEN. CLK is only recognized if CEN is active LOW.

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE2 and CE3 to select/deselect the device.

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in

conjunction with CE1 and CE3 to select/deselect the device.

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE1 and CE2 to select/deselect the device.

Output Enable, asynchronous input, active LOW. Combined with the

synchronous logic block inside the device to control the direction of the I/O pins.

When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH,

I/O pins are tri-stated, and act as input data pins. OE is masked during the data

portion of a write sequence, during the first clock when emerging from a deselected

state, when the device has been deselected.

Clock Enable Input, active LOW. When asserted LOW the Clock signal is recog-

nized by the SRAM. When deasserted HIGH the Clock signal is masked. Since

deasserting CEN does not deselect the device, CEN can be used to extend the

previous cycle when required.

ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical

“sleep” condition with data integrity preserved. During normal operation, this pin can

be connected to VSS or left floating.

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that

is triggered by the rising edge of CLK. As outputs, they deliver the data contained

in the memory location specified by the addresses presented during the previous

clock rise of the read cycle. The direction of the pins is controlled by OE. When OE

is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:D] are

placed in a tri-state condition.The outputs are automatically tri-stated during the data

portion of a write sequence, during the first clock when emerging from a deselected

state, and when the device is deselected, regardless of the state of OE.

Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to

DQs.

Mode Input. Selects the burst order of the device.

When tied to Gnd selects linear burst sequence. When tied to VDD or left floating

selects interleaved burst sequence.

Power supply inputs to the core of the device.

Power supply for the I/O circuitry.

Ground for the device.

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If

the JTAG feature is not being utilized, this pin should be left unconnected. This pin

is not available on TQFP packages.

Document #: 38-05556 Rev. *A

Page 7 of 30

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