CY7C1371D-100BZXI Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1371D-100BZXI
Cypress Semiconductor
CY7C1371D-100BZXI Datasheet PDF : 30 Pages
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PRELIMINARY
CY7C1371D
CY7C1373D
Truth Table (continued)[ 2, 3, 4, 5, 6, 7, 8]
Operation
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)
NOP/Write Abort (Begin Burst)
Write Abort (Continue Burst)
Ignore Clock Edge (Stall)
Sleep Mode
Address
Used CE1 CE2 CE3 ZZ ADV/LD WE BWX OE CEN CLK
DQ
External L H L L
L
L L X L L->H Data In (D)
Next X X X L
H
X L X L L->H Data In (D)
None L H L L
L
L H X L L->H Tri-State
Next X X X L
H
X H X L L->H Tri-State
Current X X X L
X
X X X H L->H
–
None X X X H
X
X X X X X Tri-State
Partial Truth Table for Read/Write[2, 3, 9]
Read
Function (CY7C1371D)
WE
BWA
BWB
BWC
BWD
H
X
X
X
X
Write No bytes written
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Byte C – (DQC and DQPC)
Write Byte D – (DQD and DQPD)
Write All Bytes
L
H
H
H
H
L
L
H
H
H
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
L
L
L
L
L
Partial Truth Table for Read/Write[2, 3,9]
Function (CY7C1373D)
Read
Write - No bytes written
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write All Bytes
WE
BWA
BWB
H
X
X
L
H
H
L
H
H
L
H
H
L
L
L
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1371D/CY7C1373D incorporates a serial boundary
scan test access port (TAP) in the BGA package only. The
TQFP package does not offer this functionality. This part
operates in accordance with IEEE Standard 1149.1-1900, but
doesn’t have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The
TAPoperates using JEDEC-standard 3.3V or 2.5V I/O logic
levels.
The CY7C1371D/CY7C1373D contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.
Note:
9. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write will be done based on which byte write is active.
Document #: 38-05556 Rev. *A
Page 10 of 30
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