CY7C64215(2005) Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C64215 Datasheet PDF : 26 Pages
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CY7C64215
8.0 56-Pin Part Pinout
The CY7C64215 enCoRe III device is available in a 56-pin package which is listed and illustrated in the following table. Every
port pin (labeled with a “P”) is capable of Digital IO. However, Vss and Vdd are not capable of Digital IO.
Table 8-1. 56-Pin Part Pinout (MLF*)
Pin
Type
No. Digital Analog Name
Description
CY7C64215 56-Pin enCoRe III Device
1 IO I, M P2[3] Direct switched capacitor block input.
2 IO I, M P2[1] Direct switched capacitor block input.
3 IO
M P4[7]
4 IO
M P4[5]
5 IO
M P4[3]
6 IO
M
7 IO
M
8 IO
M
9 IO
M
10 IO
M
11 IO
M
12 IO
M
13 IO
M
14 IO
M
15 IO
M
16 IO
M
17 IO
M
18 IO
M
19
Power
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
A, I, M, P2[3] 1
A, I, M, P2[1] 2
M, P4[7] 3
M, P4[5] 4
M, P4[3] 5
P5[7]
M, P4[1] 6
P5[5]
M, P3[7] 7
P5[3]
M, P3[5] 8
P5[1]
P1[7] I2C Serial Clock (SCL).
P1[5] I2C Serial Data (SDA).
P1[3]
P1[1] I2C Serial Clock (SCL), ISSP-SCLK.
Vss Ground connection.
M, P3[3] 9
M, P3[1] 10
M, P5[7] 11
M, P5[5] 12
M, P5[3] 13
M, P5[1] 14
MLF
(Top View)
42 P2[2], A, I, M
41 P2[0], A, I, M
40 P4[6], M
39 P4[4], M
38 P4[2], M
37 P4[0], M
36 P3[6], M
35 P3[4], M
34 P3[2], M
33 P3[0], M
32 P5[6], M
31 P5[4], M
30 P5[2], M
29 P5[0], M
20
USB
D+
21
USB
D-
22
Power
Vdd Supply voltage.
23 IO
P7[7]
24 IO
P7[0]
25 IO
M P1[0] I2C Serial Data (SDA), ISSP-SDATA.
26 IO
M P1[2]
27 IO
M P1[4]
28 IO
M P1[6]
29 IO
30 IO
M P5[0]
M P5[2]
Pin
Type
No. Digital Analog Name
Description
31 IO
M P5[4]
44 IO
M P2[6] External Voltage Reference (VREF) input.
32 IO
M P5[6]
45 IO I, M P0[0] Analog column mux input.
33 IO
M P3[0]
46 IO I, M P0[2] Analog column mux input and column output.
34 IO
M P3[2]
47 IO I, M P0[4] Analog column mux input and column output.
35 IO
M P3[4]
48 IO I, M P0[6] Analog column mux input.
36 IO
M P3[6]
49
Power
Vdd Supply voltage.
37 IO
M P4[0]
50
Power
Vss Ground connection.
38 IO
M P4[2]
51 IO I, M P0[7] Analog column mux input, integration input #1.
39 IO
M P4[4]
52 IO IO, M P0[5] Analog column mux input and column output,
integration input #2.
40 IO
M P4[6]
53 IO IO, M P0[3] Analog column mux input and column output.
41 IO I, M P2[0] Direct switched capacitor block input. 54 IO I, M P0[1] Analog column mux input.
42 IO I, M P2[2] Direct switched capacitor block input. 55 IO
M P2[7]
43 IO
M P2[4] External Analog Ground (AGND) in- 56 IO
put.
M P2[5]
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
* The MLF package has a center pad that must be connected to ground (Vss).
Document 38-08036 Rev. *A
Page 7 of 26
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