ISL36111DRZ-T7 Ver la hoja de datos (PDF) - Intersil
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ISL36111DRZ-T7 Datasheet PDF : 8 Pages
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ISL36111
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG. DWG. #
ISL36111DRZ-TS
6111
0 to +85
16 Ld QFN (7’’ 100 pcs.)
L16.3x3B
ISL36111DRZ-T7
6111
0 to +85
16 Ld QFN (7” 1k pcs.)
L16.3x3B
NOTES:
1. “-TS” and “-T7” suffix is for Tape and Reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL36111. For more information on MSL please
see techbrief TB363.
Pin Configuration
ISL36111
(16 LD QFN)
TOP VIEW
16 15 14 13
VDD 1
IN[P] 2
12 VDD
11 OUT[P]
IN[N] 3
10 OUT[N]
LOSB 4
9 VDD
5678
Pin Descriptions
PIN NAME
VDD
IN[P,N]
LOSB
CP[A,B,]
GND
OUT[P,N]
DT
Exposed Pad
PIN NUMBER
DESCRIPTION
1, 9, 12
Power supply. 1.2V supply voltage. The use of parallel 100pF and 10nF decoupling capacitors
to ground is recommended for each of these pins for broad high-frequency noise suppression.
2, 3
Equalizer differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
6GHz frequency response is recommended.
4
LOS BAR indicator. Low output when input signal is below DT threshold. This pin is internally
pulled HIGH with an 11kΩ resistor.
6, 7
Control pins for setting equalizer boost level. Tri-state inputs. Pins are read as a 3-digit
number to set the boost level. A is the MSB, and B is the LSB.
5, 8, 13, 16 These pins must be grounded.
11, 10
Equalizer differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
6GHz frequency response is recommended.
15
Detection Threshold. Reference DC voltage threshold for input signal power detection. Data
output OUT[P,N] is muted when the power of the input signal IN[P,N] falls below the threshold.
Tie to ground to disable electrical idle preservation and always enable the output driver.
-
Exposed pad. For proper electrical and thermal performance, this pad should be connected to
the PCB ground plane.
2
FN6974.0
November 19, 2009
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