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LH28F016SU

16M (1M × 16, 2M × 8) Flash Memory

Sharp Electronics 

LH28F016SU

16M (1M × 16, 2M × 8) Flash Memory

The LH28F016SU contains three types of Status

Registers to accomplish various functions:

• A Compatible Status Register (CSR) which is 100%

compatible with the LH28F008SA Flash memory’s

Status Register. This register, when used alone, pro-

vides a straightforward upgrade capability to the

LH28F016SU from a LH28F008SA based design.

• A Global Status Register (GSR) which informs the

system of command Queue status, Page Buffer sta-

tus, and overall Write State Machine (WSM) status.

• 32 Block Status Registers (BSRs) which provide

block-specific status information such as the block

lock-bit status.

The GSR and BSR memory maps for Byte-Wide and

Word-Wide modes are shown in Figures 5 and 6.

The LH28F016SU incorporates an open drain

RY »/BY » output pin. This feature allows the user to OR-

tie many RY/» BY» pins together in a multiple memory con-

figuration such as a Resident Flash Array.

The LH28F016SU also incorporates a dual chip-

enable function with two input pins, CE0» and CE1» .These

pins have exactly the same functionality as the regular

chip-enable pin CE » on the LH28F008SA. For minimum

chip designs, CE »1 may be tied to ground and use CE »0

as the chip enable input. The LH28F016SU uses the

logical combination of these two signals to enable or

disable the entire chip. Both CE »0 and CE »1 must be ac-

tive low to enable the device and if either one becomes

inactive, the chip will be disabled. This feature, along

with the open drain RY »/BY » pin, allows the 0system de-

signer to reduce the number of control pins used in a

large array of 16M devices.

The BYT» E» pin allows either x8 or x16 read/writes to

the LH28F016SU. BY»TE» at logic low selects 8-bit mode

with address A0 selecting between low byte and high

byte. On the other hand, BY»TE» at logic high enables

16-bit operation with address A1 becoming the lowest

order address and address A0 is not used (don’t care).

A block diagram is shown in Figure 3.

The LH28F016SU is specified for a maximum

access time of each version, as follows:

The LH28F016SU incorporates an Automatic Power

Saving (APS) feature which substantially reduces the

active current when the device is in static mode of

operation (addresses not switching).

In APS mode, the typical ICC current is 2 mA at 5.0 V

(1 mA at 3.3 V).

A Deep Power-Down mode of operation is invoked

when the RP » (called PWD on the LH28F008SA) pin

transitions low, any current operation is aborted and the

device is put into the deep power-down mode.This mode

brings the device power consumption to less than 5 µA

typically, and provides additional write protection by

acting as a device reset pin during power transitions.

When the power is turned on, RP » pin turned to low or-

der to return the device to default configuration. When

the 3/5 » pin is switched, or when the power transition is

occured, or at the power on/off, RP » is required to stay

low in order to protect data from noise. A recovery time

of 550 ns (VCC = 5.0 V ± 0.5 V) is required from RP »

switching high until outputs are again valid. In the Deep

Power-Down state, the WSM is reset (any current

operation will abort) and the CSR, GSR and BSR regis-

ters are cleared.

A CMOS Standby mode of operation is enabled when

either CE »0 or CE »1 transitions high and RP » stays high

with all input control pins at CMOS levels. In this mode,

the device typically draws an ICC standby current of

10 µA.

OPERATING

TEMPERATURE

0 - 70°C

0 - 70°C

0 - 70°C

0 - 70°C

VCC SUPPLY

4.75 - 5.25 V

4.5 - 5.5 V

3.0 - 3.6 V

2.7 - 3.6 V

MAX. ACCESS

(TACC)

70 ns

80 ns

120 ns

160 ns

6

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