ISPXPLD5512MX Ver la hoja de datos (PDF) - Lattice Semiconductor
Número de pieza
componentes Descripción
Fabricante
ISPXPLD5512MX
Lattice Semiconductor
ISPXPLD5512MX Datasheet PDF : 92 Pages
| |||
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
Table 4. MFB Memory Configuration
Memory Mode
Dual-port
Single-port, Pseudo Dual Port, FIFO
CAM
1. Smaller configurations are possible.
Max. Configuration
Size1
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 8
512 x 16
16,384 x1
8,192 x 2
4,096 x 4
2,048 x 8
1,024 x 16
512 x 32
128 x 48
Input and Output
The data input and control signals to a MFB in memory mode are generated from inputs from the routing. Data sig-
nals are only available in the true non-inverted format. True or complemented versions of the inputs are available
for generating the control signals. Data and flag outputs are fed from the MFB to the GRP and OSA. Unused inputs
and outputs are not accessible in memory mode.
ROM Operation
In each of the memory modes it is possible to specify the power-on state of each bit in the memory array. This
allows the memory to be used as ROM if desired.
Increased Depth And Width
Designs that require a memory depth or width that is greater than that support by a single MFB can be supported
by cascading multiple blocks. For dual port, single port, and pseudo dual port modes additional width is easily pro-
vided by sharing address lines. Additional depth is supported by multiplexing the RAM output. For FIFO and CAM
modes additional width is supported through the cascading of MFBs.
The Lattice design tools automatically combine blocks to support the memory size specified in the user’s design.
Bus Size Matching
All of the memory modes apart from CAM mode support different widths on each of the ports. The RAM bits are
mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of
words for each port varies this mapping scheme applies to each port.
9
Share Link: