ISPXPLD5512MX Ver la hoja de datos (PDF) - Lattice Semiconductor

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Fabricante

ISPXPLD5512MX

3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD™ Family

Lattice Semiconductor 

Lattice Semiconductor

Figure 3. MFB in SuperWIDE Logic Mode†

ispXPLD 5000MX Family Data Sheet

To Routing

68 Inputs

from

Routing

68 Inputs

from

Adjacent

MFB

Shared PT Clk

Shared PT Clk En

Shared PT Reset

Carry Out

Figure 4. Macrocell Slice in Logic Mode AND-Array

From

GRP

From Carry-in

n-7

PTOE

Sharing

68

AND Array

PTSA Bypass

PTSA

PT Clock

Shared

PT CE

Dual-OR Array

Shared PTCLK

CLK0

CLK1

CLK2

CLK3

PT Preset

PT Reset

Shared PT Reset

Global Reset

To Carry-out

n+7

DQ

Clk En

R/L

Clk

PR

Macrocell

5

PT OE to

I/O Block

From

I/O Cell

Output

to I/O Block or

Internal Control

(See Pin Table

for Assignments)

GRP

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