ISPXPLD5512MX Ver la hoja de datos (PDF) - Lattice Semiconductor

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ISPXPLD5512MX

3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD™ Family

Lattice Semiconductor 

Lattice Semiconductor

ispXPLD 5000MX Family Data Sheet

ispXPLD 5000MX Family External Switching Characteristics (Continued)1, 2, 3

Over Recommended Operating Conditions

-4

-45

-5

-52

-75

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units

Clock Frequency to RAM in:

fMAX (RAM)5

Single Port Mode

Dual Port Mode

— 155 — 155 — 155 — 155 —

— 155 — 155 — 155 — 155 —

93 MHz

93 MHz

Pseudo Dual Port Mode

— 180 — 180 — 160 — 160 — 106 MHz

fMAX (FIFO)5

tPWR_ON

Clock Frequency to FIFO

Power-on Time

— 225 — 220 — 210 — 210 — 132 MHz

— 200 — 200 — 200 — 200 — 200 µs

Timing v.1.8

1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate timing for other standards.

2. Measured using standard switching circuit, global routing loading of 1, worst case PTSA loading and 1 output switching.

3. Pulse widths and clock widths less than minimum will cause unknown behavior.

4. Standard 16-bit counter using GRP feedback.

5. CAM, FIFO, RAM fMAX specification used shared PT Clk.

30

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