MC141514T2 Ver la hoja de datos (PDF) - Motorola => Freescale

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MC141514T2

LCD Segment Driver

Motorola => Freescale 

OPERATION OF LCD DRIVER

INTRODUCTION

The MC141511 is LCD driver with selectable 1: 32 or 1: 41 multi-

plex ratios. The device consists of the following functional blocks as

shown in the Block Diagram.

CONTROL LOGIC - accepts the control signals from the MCU and

generates internal signals for synchronisation.

DISPLAY RAM - stores the display data. Each bit of the display

RAM has one-to-one correspondence to a pixel of the LCD. The display

RAM is in vertical byte oriented format as shown in Figure 6 and the

way the display RAM is addressed depends on the multiplexing mode of

the LCD (Figure 8). With reference to Figure 6, the display RAM also

contains 16 bytes of memory which is in horizontal format ($280-$28F).

The display RAM is addressed when backplane reaches 41.

LEVEL SELECTOR - consists of a switching circuit to select

appropriate voltage levels from an external voltage divider. See figure 4.

SEGMENT DRIVERS - provides the segment driving signals to the

LCD frontplane. See Figure 7.

The LCD driver clock is derived from the 2.048KHz BPCLK

and frame frequency is 64 Hz for 1:32 multiplex and 50 Hz for 1:41

multiplex ratio. See Figure 5.

GENERATION OF LCD BIAS LEVELS

Refer to Figure 4. In order to obtain optimum contrast for LCD

panels, the bias levels should be selected such that

BIAS = R/(4R+R1) = 1/( MUX + 1)

V1/VLCD = 1/( MUX + 1)

V2/VLCD = 2/( MUX + 1)

V3/VLCD = ( MUX - 1)/( MUX + 1)

V4/VLCD = MUX /( MUX + 1)

Example: Mux = 41 ----- Bias = 1: 7.4,

R = 10K, R1 = 33K, VR = 100K

Mux = 32 ----- Bias = 1: 6.6,

R = 10K, R1 = 27K, VR = 100K

MOTOROLA

MC141511A

3–27

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