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AD7883BN

LC2MOS 12-Bit, 3.3 V Sampling ADC

Analog Devices 

AD7883

The AD7883 has one unipolar input range, 0 V to VREF. Figure

4 shows the analog input for this range. The designed code

transitions occur midway between successive integer LSB val-

ues (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs . . . FS –3/2 LSBs). The

output code is straight binary with 1 LSB = FS/4096 = 3.3 V/

4096 = 0.8 mV when VREF = 3.3 V. The ideal input/output

transfer characteristic for the unipolar range is shown in Figure 6.

OUTPUT

CODE

111...111

111...110

111...101

111...100

CLOCK INPUT

The AD7883 is specified to operate with a 2 MHz clock con-

nected to the CLKIN input pin. This pin may be driven directly

by CMOS buffers. The mark/space ratio on the clock can vary

from 40/60 to 60/40. As the clock frequency is slowed down, it

can result in slightly degraded accuracy performance. This is

due to leakage effects on the hold capacitor in the internal

track-and-hold amplifier. Figure 8 is a typical plot of accuracy

versus clock frequency for the ADC.

2.5

2.0

1.5

000...011

000...010

000...001

000...000

0V 1LSB

1LSB

=

FS

4096

VIN INPUT VOLTAGE

+FS – 1LSB

Figure 6. Unipolar Transfer Characteristics

Figure 5 shows the AD7883’s ± VREF bipolar analog input con-

figuration. Once again the designed code transitions occur mid-

way between successive integer LSB values. The output code is

straight binary with 1 LSB = FS/4096 = 6.6 V/4096 = 1.6 mV.

The ideal bipolar input/output transfer characteristic is shown

in Figure 7.

OUTPUT

CODE

111...111

111...110

100...101

–FS

2

100...000

011...111

011...110

000...001

000...000

–1LSB

+1LSB

+FS – 1LSB

2

FS = 10V

1LSB = FS

4096

0V

VIN INPUT VOLTAGE

Figure 7. Bipolar Transfer Characteristic

1.0

0.5

0.0

1.0

2.0

3.0

CLOCK FREQUENCY – MHz

Figure 8. Normalized Linearity Error vs. Clock Frequency

TRACK/HOLD AMPLIFIER

The charge balanced comparator used in the AD7883 for the

A/D conversion provides the user with an inherent track/hold

function. The track/hold amplifier acquires an input signal to

12-bit accuracy in less than 5 µs. The overall throughput time is

equal to the conversion time plus the track/hold amplifier acqui-

sition time. For a 2 MHz input clock, the throughput time is

20 µs.

The operation of the track/hold amplifier is essentially transpar-

ent to the user. The track/hold amplifier goes from its tracking

mode to its hold mode at the start of conversion, i.e., on the ris-

ing edge of CONVST as shown in Figure 1.

OFFSET AND FULL-SCALE ADJUSTMENT

In most Digital Signal Processing (DSP) applications, offset and

full-scale errors have little or no effect on system performance.

Offset error can always be eliminated in the analog domain by

ac coupling. Full-scale error effect is linear and does not cause

problems as long as the input signal is within the full dynamic

range of the ADC. Some applications will require that the input

signal range match the maximum possible dynamic range of the

ADC. In such applications, offset and full-scale error will have

to be adjusted to zero.

The following sections describe suggested offset and full-scale

adjustment techniques which rely on adjusting the inherent off-

set of the op amp driving the input to the ADC as well as tweak-

ing an additional external potentiometer as shown in Figure 9.

–6–

REV. 0

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