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ADUM1400(2004) Ver la hoja de datos (PDF) - Analog Devices

Número de pieza
componentes Descripción
Fabricante
ADUM1400
(Rev.:2004)
ADI
Analog Devices ADI
ADUM1400 Datasheet PDF : 24 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADuM1400/ADuM1401/ADuM1402
Parameter
Symbol Min
ADuM140xBRW
Minimum Pulse Width3
PW
Maximum Data Rate4
10
Propagation Delay5
Pulse-Width Distortion, |tPLH – tPHL|5
tPHL, tPLH
20
PWD
Change vs. Temperature
Propagation Delay Skew6
tPSK
Channel-to-Channel Matching,
Codirectional Channels7
tPSKCD
Channel-to-Channel Matching,
Opposing-Directional Channels7
tPSKOD
ADuM140xCRW
Minimum Pulse Width3
PW
Maximum Data Rate4
90
Propagation Delay5
Pulse-Width Distortion, |tPLH – tPHL|5
tPHL, tPLH
20
PWD
Change vs. Temperature
Propagation Delay Skew6
tPSK
Channel-to-Channel Matching,
Codirectional Channels7
tPSKCD
Channel-to-Channel Matching,
Opposing-Directional Channels7
tPSKOD
For All Models
Output Disable Propagation Delay
(High/Low-to-High Impedance)
tPHZ, tPLH
Output Enable Propagation Delay
(High Impedance to High/Low)
tPZH, tPZL
Output Rise/Fall Time (10% to 90%)
tR/tF
Common-Mode Transient Immunity
at Logic High Output8
|CMH|
25
Common-Mode Transient Immunity
at Logic Low Output8
|CML|
25
Refresh Rate
Input Dynamic Supply Current, per Channel9
Output Dynamic Supply Current, per Channel9
fr
IDDI (D)
IDDO (D)
Typ Max Unit Test Conditions
100 ns
CL = 15 pF, CMOS signal levels
Mbps CL = 15 pF, CMOS signal levels
38 50 ns
CL = 15 pF, CMOS signal levels
3 ns
CL = 15 pF, CMOS signal levels
5
ps/°C CL = 15 pF, CMOS signal levels
22 ns
CL = 15 pF, CMOS signal levels
3 ns
CL = 15 pF, CMOS signal levels
6 ns
CL = 15 pF, CMOS signal levels
8.3 11.1 ns
120
Mbps
34 45 ns
0.5 2 ns
3
ps/°C
16 ns
2 ns
5 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
68
68
3
35
35
1.1
0.10
0.03
ns
CL = 15 pF, CMOS signal levels
ns
CL = 15 pF, CMOS signal levels
ns
CL = 15 pF, CMOS signal levels
kV/µs
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
kV/µs
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
Mbps
mA/Mbps
mA/Mbps
1 All voltages are relative to their respective ground.
2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on
Page 20. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11
through Figure 14 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section on Page 20 for guidance on calculating the per-channel sup-
ply current for a given data rate.
Rev. B | Page 7 of 24

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