AD7703ANZ Ver la hoja de datos (PDF) - Analog Devices

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Fabricante

AD7703ANZ

LC2MOS 20-Bit A/D Converter

Analog Devices 

AD7703

Input Voltage, Unipolar Mode

System Calibration

Self-Calibration

>(SGAIN –1.5 LSB)

>(VREF – 1.5 LSB)

SGAIN – 1.5 LSB

VREF – 1.5 LSB

Table V. Output Coding

Input Voltage, Bipolar Mode

Output Codes

FFFFF

Self-Calibration

>(VREF –1.5 LSB)

System Calibration

>(SGAIN – 1.5 LSB)

FFFFF

FFFFE

VREF – 1.5 LSB

SGAIN – 1.5 LSB

(SGAIN – SOFF)/2 – 0.5 LSB

(VREF – VAGND)/2 – 0.5 LSB

80000

7FFFF

VAGND – 0.5 LSB

SOFF – 0.5 LSB

SOFF + 0.5 LSB

<(SOFF + 0.5 LSB)

VAGND + 0.5 LSB

<(VAGND + 0.5 LSB)

00001

00000

00000

–VREF + 0.5 LSB

<(–VREF + 0.5 LSB)

–SGAIN + 2 SOFF + 0.5 LSB

<(–SGAIN +2 SOFF + 0.5 LSB)

In the Bipolar mode, the system offset calibration range is

restricted to ±0.4 VREF. It should be noted that the span restric-

tions limit the amount of offset that can be calibrated. The span

range of the converter in Bipolar mode is equidistant around the

voltage used for the zero-scale point. When the zero-scale point

is calibrated, it must not cause either of the two endpoints of the

bipolar transfer function to exceed the positive or the negative

input overrange points (+VREF + 0.1) V or (–VREF + 0.1) V. If

the span range is set to a minimum (0.8 VREF), the offset voltage

can move +0.4 VREF without causing the endpoints of the trans-

fer function to exceed the overrange points. Alternatively, if the

span range is set to 2VREF, the input offset cannot move more

than +0.1 V or –0.1 V before an endpoint of the transfer func-

tion exceeds the input overrange limit.

POWER-UP AND CALIBRATION

A calibration cycle must be carried out after power-up to initial-

ize the device to a consistent starting condition and correct

calibration. Wait for the DRDY signal to toggle low after device

power-up before initiating the first calibration sequence. The

CAL pin must be held high for at least four clock cycles, after

which calibration is initiated on the falling edge of CAL and

takes a maximum of 3,145,655 clock cycles (approximately

768 ms with a 4.096 MHz clock). See Table III.

The type of calibration cycle initiated by CAL is determined by

the SC1 and SC2 inputs, in accordance with Table III.

Drift Considerations

The AD7703 uses chopper stabilization techniques to minimize

input offset drift. Charge injection in the analog switches and

leakage currents at the sampling node are the primary sources of

offset voltage drift in the converter. Figure 13 indicates the typical

offset due to temperature changes after calibration at 25°C. Drift

is relatively flat up to 75°C. Above this temperature, leakage

current becomes the main source of offset drift. Since leakage

current doubles approximately every 10°C, the offset drifts

accordingly. The value of the voltage on the sample capacitor is

updated at a rate determined by the master clock; therefore, the

amount of offset drift that occurs will be proportional to the

elapsed time between samples. Thus, to minimize offset drift at

higher temperatures, higher CLKIN rates are recommended.

Gain drift within the converter depends mainly upon the tem-

perature tracking of the internal capacitors. It is not affected by

leakage currents so it is significantly less than offset drift. The

typical gain drift of the AD7703 is less than 40 LSB over the

specified temperature range.

Measurement errors due to offset drift or gain drift can be

eliminated at any time by recalibrating the converter. Using the

system calibration mode can also minimize offset and gain errors

in the signal conditioning circuitry. Integral and differential

linearity are not significantly affected by temperature changes.

160

CLKIN = 4.096MHz

80

0

–80

–160

–240

–320

–55 –35 –15

5 25 45 65

TEMPERATURE – ؇C

85 105 125

Figure 13. Typical Bipolar Offset vs. Temperature

after Calibration at 25°C

REV. F

–11–

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