AT32UC3A3128(2009) Ver la hoja de datos (PDF) - Atmel Corporation
Número de pieza
componentes Descripción
Fabricante
AT32UC3A3128 Datasheet PDF : 961 Pages
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AT32UC3A3
2. Overview
2.1 Block Diagram
Figure 2-1. Block Diagram
TCK
TDO
TDI
TMS
VBG
VBUS
DH+,DL+
DH-,DL-
PA
PB
PC
PX
JTAG
INTERFACE
MCKO
MDO[5..0]
MSEO[1..0]
EVTI_N
EVTO_N
NEXUS
CLASS 2+
OCD
UC CPU
MEMORY PROTECTION UNIT
INSTR
INTERFACE
DATA
INTERFACE
LOCAL BUS
INTERFACE
FAST GPIO
64 KB
SRAM
ID
VBOF
USB HS
INTERFACE
DMA
DMACA
AES
32KB RAM
32KB RAM
S
M
M
M
M
S
S
SS
M
M
S
S
HIGH SPEED
BUS MATRIX
S
S
M
CONFIGURATION REGISTERS BUS
PB
HS
HSBB-PB
BRIDGE B
HSB
HSB-PB
BRIDGE A
PB
PERIPHERAL
DMA
CONTROLLER
CLK
CMD[1..0]
DATA[15..0]
EXTINT[7..0]
KPS[7..0]
NMI_N
MULTIMEDIA CARD
& MEMORY STICK
INTERFACE
INTERRUPT
CONTROLLER
EXTERNAL
INTERRUPT
CONTROLLER
USART1
USART0
USART2
USART3
512/256/
128/64 KB
FLASH
DATA[15..0]
ADDR[23..0]
NCS[5..0]
NRD
NWAIT
NWE0
NWE1
NWE3
RAS
CAS
SDA10
SDCK
SDCKE
SDCS1
SDWE
CFCE1
CFCE2
CFRW
NANDOE
NANDWE
RXD
TXD
CLK
RTS, CTS
DSR, DTR, DCD, RI
RXD
TXD
CLK
RTS, CTS
RXD
TXD
CLK
RESET_N
115 kHz
RCOSC
XIN32 32 KHz
XOUT32 OSC
XIN0
XOUT0
OSC0
XIN1
XOUT1
OSC1
PLL0
PLL1
GCLK[3..0]
REAL TIME
COUNTER
WATCHDOG
TIMER
POWER
MANAGER
CLOCK
GENERATOR
CLOCK
CONTROLLER
SLEEP
CONTROLLER
RESET
CONTROLLER
SERIAL
PERIPHERAL
INTERFACE 0/1
SYNCHRONOUS
SERIAL
CONTROLLER
TWO-WIRE
INTERFACE 0/1
SCK
MISO, MOSI
NPCS0
NPCS[3..1]
TX_CLOCK, TX_FRAME_SYNC
TX_DATA
RX_CLOCK, RX_FRAME_SYNC
RX_DATA
SCL
SDA
ANALOG TO
DIGITAL
CONVERTER
AUDIO
BITSTREAM
DAC
AD[7..0]
DATA[1..0]
DATAN[1..0]
A[2..0]
B[2..0]
CLK[2..0]
TIMER/COUNTER
0/1
PA
PB
PC
PX
ADVREF
4
32072A–AVR32–03/09
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